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[PULL 37/37] target/riscv: Implement the stval/mtval illegal instruction
From: |
Alistair Francis |
Subject: |
[PULL 37/37] target/riscv: Implement the stval/mtval illegal instruction |
Date: |
Sat, 8 Jan 2022 15:50:48 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.
The RISC-V spec states that "The stval register can optionally also be
used to return the faulting instruction bits on an illegal instruction
exception...". In this case we are always writing the value on an
illegal instruction.
This doesn't match all CPUs (some CPUs won't write the data), but in
QEMU let's just populate the value on illegal instructions. This won't
break any guest software, but will provide more information to guests.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-4-alistair.francis@opensource.wdc.com
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 3 +++
3 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9ee01f761f..4d63086765 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -132,6 +132,8 @@ struct CPURISCVState {
target_ulong frm;
target_ulong badaddr;
+ uint32_t bins;
+
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ddacb8533a..434a83e66a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1038,6 +1038,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
write_gva = true;
tval = env->badaddr;
break;
+ case RISCV_EXCP_ILLEGAL_INST:
+ tval = env->bins;
+ break;
default:
break;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9e4f9c3342..615048ec87 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -208,6 +208,9 @@ static void generate_exception_mtval(DisasContext *ctx, int
excp)
static void gen_exception_illegal(DisasContext *ctx)
{
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+ offsetof(CPURISCVState, bins));
+
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
}
--
2.31.1
- [PULL 29/37] target/riscv: support for 128-bit arithmetic instructions, (continued)
- [PULL 29/37] target/riscv: support for 128-bit arithmetic instructions, Alistair Francis, 2022/01/08
- [PULL 24/37] target/riscv: moving some insns close to similar insns, Alistair Francis, 2022/01/08
- [PULL 28/37] target/riscv: support for 128-bit shift instructions, Alistair Francis, 2022/01/08
- [PULL 30/37] target/riscv: support for 128-bit M extension, Alistair Francis, 2022/01/08
- [PULL 31/37] target/riscv: adding high part of some csrs, Alistair Francis, 2022/01/08
- [PULL 32/37] target/riscv: helper functions to wrap calls to 128-bit csr insns, Alistair Francis, 2022/01/08
- [PULL 33/37] target/riscv: modification of the trans_csrxx for 128-bit support, Alistair Francis, 2022/01/08
- [PULL 34/37] target/riscv: actual functions to realize crs 128-bit insns, Alistair Francis, 2022/01/08
- [PULL 35/37] target/riscv: Set the opcode in DisasContext, Alistair Francis, 2022/01/08
- [PULL 36/37] target/riscv: Fixup setting GVA, Alistair Francis, 2022/01/08
- [PULL 37/37] target/riscv: Implement the stval/mtval illegal instruction,
Alistair Francis <=
- Re: [PULL 00/37] riscv-to-apply queue, Richard Henderson, 2022/01/08