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[PATCH v6 04/23] target/riscv: Improve delivery of guest external interr
From: |
Anup Patel |
Subject: |
[PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts |
Date: |
Thu, 30 Dec 2021 18:05:20 +0530 |
From: Anup Patel <anup.patel@wdc.com>
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bf50699b1f..43d6311e49 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -325,6 +325,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
}
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+
+ if (enable) {
+ /*
+ * The guest external interrupts from an interrupt controller are
+ * delivered only when the Guest/VM is running (i.e. V=1). This means
+ * any guest external interrupt which is triggered while the Guest/VM
+ * is not running (i.e. V=0) will be missed on QEMU resulting in guest
+ * with sluggish response to serial console input and other I/O events.
+ *
+ * To solve this, we check and inject interrupt after setting V=1.
+ */
+ riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+ }
}
bool riscv_cpu_two_stage_lookup(int mmu_idx)
--
2.25.1
- [PATCH v6 00/23] QEMU RISC-V AIA support, Anup Patel, 2021/12/30
- [PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2021/12/30
- [PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/12/30
- [PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2021/12/30
- [PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts,
Anup Patel <=
- [PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/12/30
- [PATCH v6 06/23] target/riscv: Add AIA cpu feature, Anup Patel, 2021/12/30
- [PATCH v6 07/23] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/12/30
- [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/12/30
- [PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/12/30
- [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/12/30
- [PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/12/30
- [PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/12/30
- [PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/12/30
- [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/12/30