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[PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and sto
From: |
frank . chang |
Subject: |
[PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns |
Date: |
Wed, 29 Dec 2021 10:33:30 +0800 |
From: Frank Chang <frank.chang@sifive.com>
All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5b47729a21..820a3387db 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -263,10 +263,19 @@ static bool vext_check_st_index(DisasContext *s, int vd,
int vs2, int nf,
uint8_t eew)
{
int8_t emul = eew - s->sew + s->lmul;
- return (emul >= -3 && emul <= 3) &&
- require_align(vs2, emul) &&
- require_align(vd, s->lmul) &&
- require_nf(vd, nf, s->lmul);
+ bool ret = (emul >= -3 && emul <= 3) &&
+ require_align(vs2, emul) &&
+ require_align(vd, s->lmul) &&
+ require_nf(vd, nf, s->lmul);
+#ifdef TARGET_RISCV32
+ /*
+ * All Zve* extensions support all vector load and store instructions,
+ * except Zve64* extensions do not support EEW=64 for index values
+ * when XLEN=32. (Section 18.2)
+ */
+ ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
+#endif
+ return ret;
}
/*
--
2.31.1
- [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions, frank . chang, 2021/12/28
- [PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, frank . chang, 2021/12/28
- [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, frank . chang, 2021/12/28
- [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns,
frank . chang <=
- [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, frank . chang, 2021/12/28
- [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, frank . chang, 2021/12/28
- [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, frank . chang, 2021/12/28
- [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, frank . chang, 2021/12/28
- [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, frank . chang, 2021/12/28
- [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, frank . chang, 2021/12/28
- [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, frank . chang, 2021/12/28
- [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, frank . chang, 2021/12/28
- [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, frank . chang, 2021/12/28
- [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, frank . chang, 2021/12/28