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[PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions
From: |
Alistair Francis |
Subject: |
[PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions |
Date: |
Mon, 20 Dec 2021 14:56:44 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-60-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aed230e1ad..cc95b69255 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3387,28 +3387,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
/* Vector Floating-Point MIN/MAX Instructions */
-RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
-RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
-RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
+RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number)
+RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number)
+RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number)
GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2)
GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4)
GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8)
-RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
-RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
-RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
+RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number)
+RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number)
+RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number)
GEN_VEXT_VF(vfmin_vf_h, 2, 2)
GEN_VEXT_VF(vfmin_vf_w, 4, 4)
GEN_VEXT_VF(vfmin_vf_d, 8, 8)
-RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
+RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number)
+RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number)
+RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number)
GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2)
GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4)
GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8)
-RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
+RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number)
+RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number)
+RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number)
GEN_VEXT_VF(vfmax_vf_h, 2, 2)
GEN_VEXT_VF(vfmax_vf_w, 4, 4)
GEN_VEXT_VF(vfmax_vf_d, 8, 8)
--
2.31.1
- [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions, (continued)
- [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions, Alistair Francis, 2021/12/20
- [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, Alistair Francis, 2021/12/20
- [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, Alistair Francis, 2021/12/20
- [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions, Alistair Francis, 2021/12/20
- [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions, Alistair Francis, 2021/12/20
- [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions, Alistair Francis, 2021/12/20
- [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, Alistair Francis, 2021/12/20
- [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, Alistair Francis, 2021/12/20
- [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, Alistair Francis, 2021/12/20
- [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, Alistair Francis, 2021/12/20
- [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions,
Alistair Francis <=
- [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions, Alistair Francis, 2021/12/20
- [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment, Alistair Francis, 2021/12/20
- [PULL 43/88] target/riscv: rvv-1.0: register gather instructions, Alistair Francis, 2021/12/20
- [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions, Alistair Francis, 2021/12/20
- [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions, Alistair Francis, 2021/12/20
- [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction, Alistair Francis, 2021/12/20
- [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, Alistair Francis, 2021/12/20
- [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32, Alistair Francis, 2021/12/20
- [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, Alistair Francis, 2021/12/20
- [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, Alistair Francis, 2021/12/20