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[PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field
From: |
Alistair Francis |
Subject: |
[PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field |
Date: |
Mon, 20 Dec 2021 14:55:47 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 12c31aa4b4..70f589813e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -98,7 +98,7 @@ static inline uint32_t vext_lmul(uint32_t desc)
static uint32_t vext_wd(uint32_t desc)
{
- return (simd_data(desc) >> 11) & 0x1;
+ return FIELD_EX32(simd_data(desc), VDATA, WD);
}
/*
--
2.31.1
- [PULL 02/88] target/riscv: zfh: half-precision computational, (continued)
- [PULL 02/88] target/riscv: zfh: half-precision computational, Alistair Francis, 2021/12/19
- [PULL 03/88] target/riscv: zfh: half-precision convert and move, Alistair Francis, 2021/12/19
- [PULL 04/88] target/riscv: zfh: half-precision floating-point compare, Alistair Francis, 2021/12/19
- [PULL 05/88] target/riscv: zfh: half-precision floating-point classify, Alistair Francis, 2021/12/19
- [PULL 06/88] target/riscv: zfh: add Zfh cpu property, Alistair Francis, 2021/12/19
- [PULL 07/88] target/riscv: zfh: implement zfhmin extension, Alistair Francis, 2021/12/19
- [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support, Alistair Francis, 2021/12/19
- [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property, Alistair Francis, 2021/12/19
- [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field, Alistair Francis, 2021/12/19
- [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, Alistair Francis, 2021/12/19
- [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field,
Alistair Francis <=
- [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field, Alistair Francis, 2021/12/19
- [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field, Alistair Francis, 2021/12/19
- [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status, Alistair Francis, 2021/12/19
- [PULL 17/88] target/riscv: rvv-1.0: add vcsr register, Alistair Francis, 2021/12/19
- [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, Alistair Francis, 2021/12/19
- [PULL 18/88] target/riscv: rvv-1.0: add vlenb register, Alistair Francis, 2021/12/19
- [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, Alistair Francis, 2021/12/19
- [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL, Alistair Francis, 2021/12/19
- [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations, Alistair Francis, 2021/12/19
- [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA, Alistair Francis, 2021/12/19