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[PATCH 05/20] tcg/i386: Detect AVX512
From: |
Richard Henderson |
Subject: |
[PATCH 05/20] tcg/i386: Detect AVX512 |
Date: |
Sat, 18 Dec 2021 11:42:35 -0800 |
There are some operation sizes in some subsets of AVX512 that
are missing from previous iterations of AVX. Detect them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/cpuid.h | 20 +++++++++++++++++---
tcg/i386/tcg-target.h | 4 ++++
tcg/i386/tcg-target.c.inc | 24 ++++++++++++++++++++++--
3 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 09fc245b91..7adb12d320 100644
--- a/include/qemu/cpuid.h
+++ b/include/qemu/cpuid.h
@@ -45,12 +45,26 @@
#ifndef bit_AVX2
#define bit_AVX2 (1 << 5)
#endif
-#ifndef bit_AVX512F
-#define bit_AVX512F (1 << 16)
-#endif
#ifndef bit_BMI2
#define bit_BMI2 (1 << 8)
#endif
+#ifndef bit_AVX512F
+#define bit_AVX512F (1 << 16)
+#endif
+#ifndef bit_AVX512DQ
+#define bit_AVX512DQ (1 << 17)
+#endif
+#ifndef bit_AVX512BW
+#define bit_AVX512BW (1 << 30)
+#endif
+#ifndef bit_AVX512VL
+#define bit_AVX512VL (1u << 31)
+#endif
+
+/* Leaf 7, %ecx */
+#ifndef bit_AVX512VBMI2
+#define bit_AVX512VBMI2 (1 << 6)
+#endif
/* Leaf 0x80000001, %ecx */
#ifndef bit_LZCNT
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 64c1013182..12d098ad6c 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -103,6 +103,10 @@ extern bool have_bmi1;
extern bool have_popcnt;
extern bool have_avx1;
extern bool have_avx2;
+extern bool have_avx512bw;
+extern bool have_avx512dq;
+extern bool have_avx512vbmi2;
+extern bool have_avx512vl;
extern bool have_movbe;
/* optional instructions */
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 84b109bb84..e266f937d6 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -170,6 +170,10 @@ bool have_bmi1;
bool have_popcnt;
bool have_avx1;
bool have_avx2;
+bool have_avx512bw;
+bool have_avx512dq;
+bool have_avx512vbmi2;
+bool have_avx512vl;
bool have_movbe;
#ifdef CONFIG_CPUID_H
@@ -3746,12 +3750,12 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int
count)
static void tcg_target_init(TCGContext *s)
{
#ifdef CONFIG_CPUID_H
- unsigned a, b, c, d, b7 = 0;
+ unsigned a, b, c, d, b7 = 0, c7 = 0;
int max = __get_cpuid_max(0, 0);
if (max >= 7) {
/* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
- __cpuid_count(7, 0, a, b7, c, d);
+ __cpuid_count(7, 0, a, b7, c7, d);
have_bmi1 = (b7 & bit_BMI) != 0;
have_bmi2 = (b7 & bit_BMI2) != 0;
}
@@ -3781,6 +3785,22 @@ static void tcg_target_init(TCGContext *s)
if ((xcrl & 6) == 6) {
have_avx1 = (c & bit_AVX) != 0;
have_avx2 = (b7 & bit_AVX2) != 0;
+
+ /*
+ * There are interesting instructions in AVX512, so long
+ * as we have AVX512VL, which indicates support for EVEX
+ * on sizes smaller than 512 bits. We are required to
+ * check that OPMASK and all extended ZMM state are enabled
+ * even if we're not using them -- the insns will fault.
+ */
+ if ((xcrl & 0xe0) == 0xe0
+ && (b7 & bit_AVX512F)
+ && (b7 & bit_AVX512VL)) {
+ have_avx512vl = true;
+ have_avx512bw = (b7 & bit_AVX512BW) != 0;
+ have_avx512dq = (b7 & bit_AVX512DQ) != 0;
+ have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0;
+ }
}
}
}
--
2.25.1
- [PATCH 00/20] tcg: vector improvements, Richard Henderson, 2021/12/18
- [PATCH 01/20] tcg/optimize: Fix folding of vector ops, Richard Henderson, 2021/12/18
- [PATCH 04/20] tcg/s390x: Implement vector NAND, NOR, EQV, Richard Henderson, 2021/12/18
- [PATCH 02/20] tcg: Add opcodes for vector nand, nor, eqv, Richard Henderson, 2021/12/18
- [PATCH 03/20] tcg/ppc: Implement vector NAND, NOR, EQV, Richard Henderson, 2021/12/18
- [PATCH 05/20] tcg/i386: Detect AVX512,
Richard Henderson <=
- [PATCH 06/20] tcg/i386: Add tcg_out_evex_opc, Richard Henderson, 2021/12/18
- [PATCH 07/20] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv, Richard Henderson, 2021/12/18
- [PATCH 08/20] tcg/i386: Implement avx512 variable shifts, Richard Henderson, 2021/12/18
- [PATCH 09/20] tcg/i386: Implement avx512 scalar shift, Richard Henderson, 2021/12/18
- [PATCH 11/20] tcg/i386: Implement avx512 immediate rotate, Richard Henderson, 2021/12/18
- [PATCH 13/20] tcg/i386: Support avx512vbmi2 vector shift-double instructions, Richard Henderson, 2021/12/18
- [PATCH 10/20] tcg/i386: Implement avx512 immediate sari shift, Richard Henderson, 2021/12/18
- [PATCH 12/20] tcg/i386: Implement avx512 variable rotate, Richard Henderson, 2021/12/18
- [PATCH 15/20] tcg/i386: Remove rotls_vec from tcg_target_op_def, Richard Henderson, 2021/12/18
- [PATCH 14/20] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double, Richard Henderson, 2021/12/18