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Re: [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ire
From: |
Alistair Francis |
Subject: |
Re: [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback |
Date: |
Fri, 17 Dec 2021 13:17:04 +1000 |
On Sat, Dec 11, 2021 at 2:26 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The AIA device emulation (such as AIA IMSIC) should be able to set
> (or provide) AIA ireg read-modify-write callback for each privilege
> level of a RISC-V HART.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 23 +++++++++++++++++++++++
> target/riscv/cpu_helper.c | 14 ++++++++++++++
> 2 files changed, 37 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6e5b6acd44..df1d792951 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -240,6 +240,22 @@ struct CPURISCVState {
> uint64_t (*rdtime_fn)(uint32_t);
> uint32_t rdtime_fn_arg;
>
> + /* machine specific AIA ireg read-modify-write callback */
> +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
> + ((((__xlen) & 0xff) << 24) | \
> + (((__vgein) & 0x3f) << 20) | \
> + (((__virt) & 0x1) << 18) | \
> + (((__priv) & 0x3) << 16) | \
> + (__isel & 0xffff))
> +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
> +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
> +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1)
> +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f)
> +#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff)
> + int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
> + target_ulong *val, target_ulong new_val, target_ulong write_mask);
> + void *aia_ireg_rmw_fn_arg[4];
> +
> /* True if in debugger mode. */
> bool debugger;
>
> @@ -391,6 +407,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t
> mask, uint32_t value);
> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
> uint32_t arg);
> +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
> + int (*rmw_fn)(void *arg,
> + target_ulong reg,
> + target_ulong *val,
> + target_ulong new_val,
> + target_ulong write_mask),
> + void *rmw_fn_arg);
> #endif
> void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 1fa9f0e584..57c07ba1a4 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -364,6 +364,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env,
> uint64_t (*fn)(uint32_t),
> env->rdtime_fn_arg = arg;
> }
>
> +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
> + int (*rmw_fn)(void *arg,
> + target_ulong reg,
> + target_ulong *val,
> + target_ulong new_val,
> + target_ulong write_mask),
> + void *rmw_fn_arg)
> +{
> + if (priv <= PRV_M) {
> + env->aia_ireg_rmw_fn[priv] = rmw_fn;
> + env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
> + }
> +}
> +
> void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> {
> if (newpriv > PRV_M) {
> --
> 2.25.1
>
>
- [PATCH v5 00/23] QEMU RISC-V AIA support, Anup Patel, 2021/12/10
- [PATCH v5 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2021/12/10
- [PATCH v5 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/12/10
- [PATCH v5 03/23] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2021/12/10
- [PATCH v5 04/23] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2021/12/10
- [PATCH v5 05/23] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/12/10
- [PATCH v5 06/23] target/riscv: Add AIA cpu feature, Anup Patel, 2021/12/10
- [PATCH v5 07/23] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/12/10
- [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2021/12/10
- Re: [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback,
Alistair Francis <=
- [PATCH v5 09/23] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/12/10
- [PATCH v5 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/12/10
- [PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/12/10
- [PATCH v5 12/23] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/12/10
- [PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/12/10