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[PULL 084/101] target/ppc: PMU: update counters on MMCR1 write
From: |
Cédric Le Goater |
Subject: |
[PULL 084/101] target/ppc: PMU: update counters on MMCR1 write |
Date: |
Thu, 16 Dec 2021 21:25:57 +0100 |
From: Daniel Henrique Barboza <danielhb413@gmail.com>
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PMU that we're modeling, also uses MMCRA, MMCR2 and MMCR3 to
control the PMU. These three registers aren't being handled in this
initial implementation, so for now we're controlling all the PMU
aspects using MMCR0, MMCR1 and the PMCs.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 2 +-
target/ppc/power8-pmu.c | 7 +++++++
target/ppc/power8-pmu-regs.c.inc | 11 +++++++++++
5 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 984d03181a52..77c85e1292fa 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -21,6 +21,7 @@ DEF_HELPER_1(hrfid, void, env)
DEF_HELPER_2(store_lpcr, void, env, tl)
DEF_HELPER_2(store_pcr, void, env, tl)
DEF_HELPER_2(store_mmcr0, void, env, tl)
+DEF_HELPER_2(store_mmcr1, void, env, tl)
DEF_HELPER_3(store_pmc, void, env, i32, i64)
DEF_HELPER_2(read_pmc, tl, env, i32)
#endif
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 1e79a0522aac..1d6521eedc83 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ceb325b311fb..e865d368f237 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6258,7 +6258,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
KVM_REG_PPC_MMCR0, 0x80000000);
spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_MMCR1,
KVM_REG_PPC_MMCR1, 0x00000000);
spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 7131f52ccc5d..73252529beee 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -133,6 +133,13 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong
value)
hreg_compute_hflags(env);
}
+void helper_store_mmcr1(CPUPPCState *env, uint64_t value)
+{
+ pmu_update_cycles(env);
+
+ env->spr[SPR_POWER_MMCR1] = value;
+}
+
target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn)
{
pmu_update_cycles(env);
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index f0c9cc343b3d..25b13ad56434 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -255,6 +255,12 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
{
write_MMCR0_common(ctx, cpu_gpr[gprn]);
}
+
+void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_icount_io_start(ctx);
+ gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]);
+}
#else
void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)
{
@@ -301,6 +307,11 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
spr_write_generic(ctx, sprn, gprn);
}
+void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
+{
+ spr_write_generic(ctx, sprn, gprn);
+}
+
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
{
spr_write_generic(ctx, sprn, gprn);
--
2.31.1
- [PULL 057/101] target/ppc: Fix MPCxxx FPU interrupt address, (continued)
- [PULL 057/101] target/ppc: Fix MPCxxx FPU interrupt address, Cédric Le Goater, 2021/12/16
- [PULL 086/101] target/ppc: enable PMU instruction count, Cédric Le Goater, 2021/12/16
- [PULL 097/101] ppc/pnv: Introduce a num_stack class attribute, Cédric Le Goater, 2021/12/16
- [PULL 098/101] ppc/pnv: Compute the PHB index from the PHB4 PEC model, Cédric Le Goater, 2021/12/16
- [PULL 100/101] ppc/pnv: Move realize of PEC stacks under the PEC model, Cédric Le Goater, 2021/12/16
- [PULL 099/101] ppc/pnv: Remove "system-memory" property from PHB4 PEC, Cédric Le Goater, 2021/12/16
- [PULL 095/101] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices, Cédric Le Goater, 2021/12/16
- [PULL 093/101] ppc/pnv: Use QOM hierarchy to scan PHB3 devices, Cédric Le Goater, 2021/12/16
- [PULL 090/101] ppc/pnv: Use the chip class to check the index of PHB3 devices, Cédric Le Goater, 2021/12/16
- [PULL 101/101] ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices, Cédric Le Goater, 2021/12/16
- [PULL 084/101] target/ppc: PMU: update counters on MMCR1 write,
Cédric Le Goater <=
- [PULL 089/101] ppc/pnv: Introduce a "chip" property under PHB3, Cédric Le Goater, 2021/12/16
- [PULL 094/101] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices, Cédric Le Goater, 2021/12/16
- [PULL 079/101] target/ppc: Fix e6500 boot, Cédric Le Goater, 2021/12/16
- Re: [PULL v2 000/101] ppc queue, Richard Henderson, 2021/12/17