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[PULL 074/101] ppc/ppc405: Add update of bi_procfreq field
From: |
Cédric Le Goater |
Subject: |
[PULL 074/101] ppc/ppc405: Add update of bi_procfreq field |
Date: |
Thu, 16 Dec 2021 21:25:47 +0100 |
Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_uc.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2a1e2d71b08b..ec97b22bd019 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -102,12 +102,13 @@ static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env,
ppc4xx_bd_info_t *bd)
for (i = 0; i < 32; i++) {
stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
}
- stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
- stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
+ stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
- stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+ stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
}
- n = 0x6A;
+ n = 0x70; /* includes 2 bytes hole */
for (i = 0; i < 6; i++) {
stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
--
2.31.1
- [PULL 063/101] ppc: Add trace-events for DCR accesses, (continued)
- [PULL 063/101] ppc: Add trace-events for DCR accesses, Cédric Le Goater, 2021/12/16
- [PULL 069/101] ppc/ppc405: Rework FW load, Cédric Le Goater, 2021/12/16
- [PULL 073/101] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information, Cédric Le Goater, 2021/12/16
- [PULL 076/101] target/ppc: Move xs{max,min}[cj]dp to decodetree, Cédric Le Goater, 2021/12/16
- [PULL 092/101] ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize(), Cédric Le Goater, 2021/12/16
- [PULL 087/101] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Cédric Le Goater, 2021/12/16
- [PULL 083/101] target/ppc: PMU: update counters on PMCs r/w, Cédric Le Goater, 2021/12/16
- [PULL 091/101] ppc/pnv: Drop the "num-phbs" property, Cédric Le Goater, 2021/12/16
- [PULL 096/101] ppc/pnv: Introduce a "chip" property under the PHB4 model, Cédric Le Goater, 2021/12/16
- [PULL 082/101] target/ppc: PMU basic cycle count for pseries TCG, Cédric Le Goater, 2021/12/16
- [PULL 074/101] ppc/ppc405: Add update of bi_procfreq field,
Cédric Le Goater <=
- [PULL 072/101] ppc/ppc405: Change default PLL values at reset, Cédric Le Goater, 2021/12/16
- [PULL 066/101] ppc/ppc405: Change ppc405ep_init() return value, Cédric Le Goater, 2021/12/16
- [PULL 067/101] ppc/ppc405: Add some address space definitions, Cédric Le Goater, 2021/12/16
- [PULL 088/101] PPC64/TCG: Implement 'rfebb' instruction, Cédric Le Goater, 2021/12/16
- [PULL 085/101] target/ppc: enable PMU counter overflow with cycle events, Cédric Le Goater, 2021/12/16
- [PULL 057/101] target/ppc: Fix MPCxxx FPU interrupt address, Cédric Le Goater, 2021/12/16
- [PULL 086/101] target/ppc: enable PMU instruction count, Cédric Le Goater, 2021/12/16
- [PULL 097/101] ppc/pnv: Introduce a num_stack class attribute, Cédric Le Goater, 2021/12/16
- [PULL 098/101] ppc/pnv: Compute the PHB index from the PHB4 PEC model, Cédric Le Goater, 2021/12/16
- [PULL 100/101] ppc/pnv: Move realize of PEC stacks under the PEC model, Cédric Le Goater, 2021/12/16