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[PULL 080/101] Revert "target/ppc: Move SPR_DSISR setting to powerpc_exc
From: |
Cédric Le Goater |
Subject: |
[PULL 080/101] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp" |
Date: |
Thu, 16 Dec 2021 21:25:53 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TCG code in powerpc_excp because some kvm-only
routines use it indirectly to dispatch interrupts. See
kvm_handle_debug, spapr_mce_req_event and
spapr_do_system_reset_on_cpu.
We can re-introduce the change once we have split the interrupt
injection code between KVM and TCG.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index feb3fd42e26c..6ba0840e9935 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -464,15 +464,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
/*
- * Get rS/rD and rA from faulting opcode.
- * Note: We will only invoke ALIGN for atomic operations,
- * so all instructions are X-form.
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
*/
- {
- uint32_t insn = cpu_ldl_code(env, env->nip);
- env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16;
- }
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
@@ -1441,6 +1439,11 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr
vaddr,
int mmu_idx, uintptr_t retaddr)
{
CPUPPCState *env = cs->env_ptr;
+ uint32_t insn;
+
+ /* Restore state and reload the insn we executed, for filling in DSISR. */
+ cpu_restore_state(cs, retaddr, true);
+ insn = cpu_ldl_code(env, env->nip);
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_4xx:
@@ -1456,8 +1459,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr
vaddr,
}
cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = 0;
- cpu_loop_exit_restore(cs, retaddr);
+ env->error_code = insn & 0x03FF0000;
+ cpu_loop_exit(cs);
}
#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
--
2.31.1
- [PULL 022/101] softfloat: Add flag specific to Inf * 0, (continued)
- [PULL 022/101] softfloat: Add flag specific to Inf * 0, Cédric Le Goater, 2021/12/16
- [PULL 032/101] target/ppc: Fix VXCVI return value, Cédric Le Goater, 2021/12/16
- [PULL 043/101] target/ppc: Update sqrt for new flags, Cédric Le Goater, 2021/12/16
- [PULL 050/101] target/ppc: Add helper for fmuls, Cédric Le Goater, 2021/12/16
- [PULL 047/101] target/ppc: Add helpers for fmadds et al, Cédric Le Goater, 2021/12/16
- [PULL 054/101] target/ppc: Disable software TLB for the 7450 family, Cédric Le Goater, 2021/12/16
- [PULL 060/101] target/ppc: remove 401/403 CPUs, Cédric Le Goater, 2021/12/16
- [PULL 062/101] ppc: Mark the 'taihu' machine as deprecated, Cédric Le Goater, 2021/12/16
- [PULL 064/101] ppc/ppc405: Convert printfs to trace-events, Cédric Le Goater, 2021/12/16
- [PULL 058/101] target/ppc: Remove 603e exception model, Cédric Le Goater, 2021/12/16
- [PULL 080/101] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp",
Cédric Le Goater <=
- [PULL 070/101] ppc/ppc405: Introduce ppc405_set_default_bootinfo(), Cédric Le Goater, 2021/12/16
- [PULL 078/101] target/ppc: move xscvqpdp to decodetree, Cédric Le Goater, 2021/12/16
- [PULL 065/101] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo(), Cédric Le Goater, 2021/12/16
- [PULL 081/101] target/ppc: introduce PMUEventType and PMU overflow timers, Cédric Le Goater, 2021/12/16
- [PULL 075/101] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers, Cédric Le Goater, 2021/12/16
- [PULL 059/101] target/ppc: Set 601v exception model id, Cédric Le Goater, 2021/12/16
- [PULL 071/101] ppc/ppc405: Fix boot from kernel, Cédric Le Goater, 2021/12/16
- [PULL 063/101] ppc: Add trace-events for DCR accesses, Cédric Le Goater, 2021/12/16
- [PULL 069/101] ppc/ppc405: Rework FW load, Cédric Le Goater, 2021/12/16
- [PULL 073/101] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information, Cédric Le Goater, 2021/12/16