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[PATCH v2 0/9] A collection of RISC-V cleanups and improvements
From: |
Alistair Francis |
Subject: |
[PATCH v2 0/9] A collection of RISC-V cleanups and improvements |
Date: |
Thu, 16 Dec 2021 14:54:18 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
This is a few patches to cleanup some RISC-V hardware and mark the
Hyperisor extension as non experimental.
v2:
- Add some more fixes
- Address review comments
Alistair Francis (9):
hw/intc: sifive_plic: Add a reset function
hw/intc: sifive_plic: Cleanup the write function
hw/intc: sifive_plic: Cleanup the read function
hw/intc: sifive_plic: Cleanup remaining functions
target/riscv: Mark the Hypervisor extension as non experimental
target/riscv: Enable the Hypervisor extension by default
hw/riscv: Use error_fatal for SoC realisation
hw/riscv: virt: Allow support for 32 cores
hw/riscv: virt: Set the clock-frequency
include/hw/riscv/virt.h | 2 +-
hw/intc/sifive_plic.c | 254 +++++++++++--------------------------
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/opentitan.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/virt.c | 1 +
target/riscv/cpu.c | 2 +-
8 files changed, 83 insertions(+), 184 deletions(-)
--
2.31.1
- [PATCH v2 0/9] A collection of RISC-V cleanups and improvements,
Alistair Francis <=
- [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2021/12/15
- [PATCH v2 2/9] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2021/12/15
- [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/12/15
- [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2021/12/15
- [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2021/12/15