[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 06/12] hw/dma/xlnx_csu_dma: Implement the DMA control interfac
From: |
Francisco Iglesias |
Subject: |
[PATCH v5 06/12] hw/dma/xlnx_csu_dma: Implement the DMA control interface |
Date: |
Tue, 14 Dec 2021 11:03:48 +0000 |
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
---
hw/dma/xlnx_csu_dma.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
index 896bb3574d..8382aa526f 100644
--- a/hw/dma/xlnx_csu_dma.c
+++ b/hw/dma/xlnx_csu_dma.c
@@ -30,6 +30,7 @@
#include "hw/stream.h"
#include "hw/register.h"
#include "hw/dma/xlnx_csu_dma.h"
+#include "hw/dma/dma-ctrl-if.h"
/*
* Ref: UG1087 (v1.7) February 8, 2019
@@ -472,6 +473,19 @@ static uint64_t addr_msb_pre_write(RegisterInfo *reg,
uint64_t val)
return val & R_ADDR_MSB_ADDR_MSB_MASK;
}
+static void xlnx_csu_dma_dma_ctrl_if_read(DmaCtrlIf *dma, hwaddr addr,
+ uint32_t len)
+{
+ XlnxCSUDMA *s = XLNX_CSU_DMA(dma);
+ RegisterInfo *reg = &s->regs_info[R_SIZE];
+ uint64_t we = MAKE_64BIT_MASK(0, 4 * 8);
+
+ s->regs[R_ADDR] = addr;
+ s->regs[R_ADDR_MSB] = (uint64_t)addr >> 32;
+
+ register_write(reg, len, we, object_get_typename(OBJECT(s)), false);
+}
+
static const RegisterAccessInfo *xlnx_csu_dma_regs_info[] = {
#define DMACH_REGINFO(NAME, snd) \
(const RegisterAccessInfo []) { \
@@ -696,6 +710,7 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass,
void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
+ DmaCtrlIfClass *dcic = DMA_CTRL_IF_CLASS(klass);
dc->reset = xlnx_csu_dma_reset;
dc->realize = xlnx_csu_dma_realize;
@@ -704,6 +719,8 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass,
void *data)
ssc->push = xlnx_csu_dma_stream_push;
ssc->can_push = xlnx_csu_dma_stream_can_push;
+
+ dcic->read = xlnx_csu_dma_dma_ctrl_if_read;
}
static void xlnx_csu_dma_init(Object *obj)
@@ -731,6 +748,7 @@ static const TypeInfo xlnx_csu_dma_info = {
.instance_init = xlnx_csu_dma_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK },
+ { TYPE_DMA_CTRL_IF },
{ }
}
};
--
2.11.0
- [PATCH v5 00/12] Xilinx Versal's PMC SLCR and OSPI support, Francisco Iglesias, 2021/12/14
- [PATCH v5 02/12] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models, Francisco Iglesias, 2021/12/14
- [PATCH v5 01/12] hw/misc: Add a model of Versal's PMC SLCR, Francisco Iglesias, 2021/12/14
- [PATCH v5 05/12] hw/dma: Add the DMA control interface, Francisco Iglesias, 2021/12/14
- [PATCH v5 06/12] hw/dma/xlnx_csu_dma: Implement the DMA control interface,
Francisco Iglesias <=
- [PATCH v5 09/12] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g, Francisco Iglesias, 2021/12/14
- [PATCH v5 10/12] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI, Francisco Iglesias, 2021/12/14
- [PATCH v5 07/12] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller, Francisco Iglesias, 2021/12/14
- [PATCH v5 03/12] hw/arm/xlnx-versal: Connect Versal's PMC SLCR, Francisco Iglesias, 2021/12/14
- [PATCH v5 04/12] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header, Francisco Iglesias, 2021/12/14
- [PATCH v5 11/12] MAINTAINERS: Add an entry for Xilinx Versal OSPI, Francisco Iglesias, 2021/12/14
- [PATCH v5 12/12] docs/devel: Add documentation for the DMA control interface, Francisco Iglesias, 2021/12/14
- [PATCH v5 08/12] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model, Francisco Iglesias, 2021/12/14