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[PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in H
From: |
Anup Patel |
Subject: |
[PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in HART |
Date: |
Sat, 11 Dec 2021 09:49:11 +0530 |
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 +++++
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 916319afcd..4042839785 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -463,6 +463,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
}
+ if (cpu->cfg.aia) {
+ riscv_set_feature(env, RISCV_FEATURE_AIA);
+ }
+
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@@ -689,6 +693,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+ DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a43e38dd2e..d03a90e277 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -357,6 +357,7 @@ struct RISCVCPU {
bool mmu;
bool pmp;
bool epmp;
+ bool aia;
uint64_t resetvec;
} cfg;
};
--
2.25.1
- Re: [PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs, (continued)
- [PATCH v5 12/23] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/12/10
- [PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/12/10
- [PATCH v5 14/23] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/12/10
- [PATCH v5 15/23] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/12/10
- [PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2021/12/10
- [PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in HART,
Anup Patel <=
- [PATCH v5 18/23] hw/intc: Add RISC-V AIA APLIC device emulation, Anup Patel, 2021/12/10
- [PATCH v5 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Anup Patel, 2021/12/10
- [PATCH v5 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation, Anup Patel, 2021/12/10
- [PATCH v5 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Anup Patel, 2021/12/10
- [PATCH v5 22/23] docs/system: riscv: Document AIA options for virt machine, Anup Patel, 2021/12/10
- [PATCH v5 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs, Anup Patel, 2021/12/10