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[PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction
From: |
frank . chang |
Subject: |
[PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction |
Date: |
Fri, 10 Dec 2021 15:56:58 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d7c6bc9af2..3b6524bad9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -79,6 +79,7 @@
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -672,6 +673,7 @@ vsext_vf4 010010 . ..... 00101 010 ..... 1010111
@r2_vm
vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
+vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32 Zba Standard Extension ***
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index ff8f6df8f7..e540b5d33c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -160,6 +160,26 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,
TCGv s2)
return true;
}
+static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
+{
+ TCGv dst;
+
+ if (!require_rvv(s) || !has_ext(s, RVV)) {
+ return false;
+ }
+
+ dst = dest_gpr(s, rd);
+
+ gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_set_gpr(s, rd, dst);
+ mark_vs_dirty(s);
+ tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
+ tcg_gen_lookup_and_goto_ptr();
+ s->base.is_jmp = DISAS_NORETURN;
+
+ return true;
+}
+
static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
{
TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO);
@@ -172,6 +192,13 @@ static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
return do_vsetvl(s, a->rd, a->rs1, s2);
}
+static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
+{
+ TCGv s1 = tcg_const_tl(a->rs1);
+ TCGv s2 = tcg_const_tl(a->zimm);
+ return do_vsetivli(s, a->rd, s1, s2);
+}
+
/* vector register offset from env */
static uint32_t vreg_ofs(DisasContext *s, int reg)
{
--
2.31.1
- [PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, (continued)
- [PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/12/10
- [PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/12/10
- [PATCH v11 66/77] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/12/10
- [PATCH v11 68/77] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/12/10
- [PATCH v11 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/12/10
- [PATCH v11 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/12/10
- [PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/12/10
- [PATCH v11 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/12/10
- [PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction,
frank . chang <=
- [PATCH v11 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/12/10
- [PATCH v11 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/12/10
- [PATCH v11 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 2021/12/10
- [PATCH v11 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/12/10
- [PATCH v11 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 2021/12/10
- Re: [PATCH v11 00/77] support vector extension v1.0, Alistair Francis, 2021/12/16