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[PATCH v11 09/77] target/riscv: rvv-1.0: add vcsr register
From: |
frank . chang |
Subject: |
[PATCH v11 09/77] target/riscv: rvv-1.0: add vcsr register |
Date: |
Fri, 10 Dec 2021 15:55:55 +0800 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 7 +++++++
target/riscv/csr.c | 17 +++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index bb62da7549..8dc6aa62c6 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -60,9 +60,16 @@
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
+#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+/* VCSR fields */
+#define VCSR_VXSAT_SHIFT 0
+#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
+
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c522260986..832ccdcf33 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -336,6 +336,22 @@ static RISCVException write_vstart(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
+ return RISCV_EXCP_NONE;
+}
+
+static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->mstatus |= MSTATUS_VS;
+#endif
+ env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
+ env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
+ return RISCV_EXCP_NONE;
+}
+
/* User Timers and Counters */
static RISCVException read_instret(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -1816,6 +1832,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
+ [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
/* User Timers and Counters */
--
2.31.1
- [PATCH v11 00/77] support vector extension v1.0, frank . chang, 2021/12/10
- [PATCH v11 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/12/10
- [PATCH v11 02/77] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/12/10
- [PATCH v11 03/77] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/12/10
- [PATCH v11 06/77] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/12/10
- [PATCH v11 05/77] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/12/10
- [PATCH v11 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, frank . chang, 2021/12/10
- [PATCH v11 07/77] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/12/10
- [PATCH v11 09/77] target/riscv: rvv-1.0: add vcsr register,
frank . chang <=
- [PATCH v11 10/77] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/12/10
- [PATCH v11 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/12/10
- [PATCH v11 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/12/10
- [PATCH v11 12/77] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/12/10
- [PATCH v11 15/77] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/12/10
- [PATCH v11 14/77] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/12/10
- [PATCH v11 16/77] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/12/10
- [PATCH v11 13/77] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/12/10
- [PATCH v11 18/77] target/riscv: rvv-1.0: remove amo operations instructions, frank . chang, 2021/12/10
- [PATCH v11 20/77] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/12/10