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[PATCH v3 7/9] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
From: |
Tong Ho |
Subject: |
[PATCH v3 7/9] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device |
Date: |
Thu, 16 Sep 2021 22:23:58 -0700 |
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)
The command argument:
-drive if=pflash,index=2,...
Can be used to optionally connect the bbram to a backend
storage, such that field-programmed values in one
invocation can be made available to next invocation.
The backend storage must be a seekable binary file, and
its size must be 36 bytes or larger. A file with all
binary 0's is a 'blank'.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/Kconfig | 1 +
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 2 ++
4 files changed, 38 insertions(+)
diff --git a/hw/Kconfig b/hw/Kconfig
index 8cb7664d70..b6fb6a4507 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -81,3 +81,4 @@ config XLNX_ZYNQMP
select REGISTER
select CAN_BUS
select PTIMER
+ select XLNX_BBRAM
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 6c6cb02e86..b247c5779b 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -98,6 +98,18 @@ static void zcu102_modify_dtb(const struct arm_boot_info
*binfo, void *fdt)
}
}
+static void bbram_attach_drive(XlnxBBRam *dev)
+{
+ DriveInfo *dinfo;
+ BlockBackend *blk;
+
+ dinfo = drive_get_by_index(IF_PFLASH, 2);
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
+ if (blk) {
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
+ }
+}
+
static void xlnx_zcu102_init(MachineState *machine)
{
XlnxZCU102 *s = ZCU102_MACHINE(machine);
@@ -136,6 +148,9 @@ static void xlnx_zcu102_init(MachineState *machine)
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
+ /* Attach bbram backend, if given */
+ bbram_attach_drive(&s->soc.bbram);
+
/* Create and plug in the SD cards */
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
BusState *bus;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 4e5a471e30..1e8e2ddcc2 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -66,6 +66,9 @@
#define RTC_ADDR 0xffa60000
#define RTC_IRQ 26
+#define BBRAM_ADDR 0xffcd0000
+#define BBRAM_IRQ 11
+
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
@@ -226,6 +229,22 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms,
XlnxZynqMPState *s,
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
}
+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
+ sizeof(s->bbram), TYPE_XLNX_BBRAM,
+ &error_fatal,
+ "crc-zpads", "1",
+ NULL);
+ sbd = SYS_BUS_DEVICE(&s->bbram);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
+}
+
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
{
static const struct UnimpInfo {
@@ -626,6 +645,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
+ xlnx_zynqmp_create_bbram(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index c84fe15996..067e8a5238 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -36,6 +36,7 @@
#include "qom/object.h"
#include "net/can_emu.h"
#include "hw/dma/xlnx_csu_dma.h"
+#include "hw/nvram/xlnx-bbram.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -100,6 +101,7 @@ struct XlnxZynqMPState {
MemoryRegion *ddr_ram;
MemoryRegion ddr_ram_low, ddr_ram_high;
+ XlnxBBRam bbram;
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
--
2.25.1
- [PATCH v3 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM, Tong Ho, 2021/09/17
- [PATCH v3 5/9] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device, Tong Ho, 2021/09/17
- [PATCH v3 2/9] hw/nvram: Introduce Xilinx Versal eFuse device, Tong Ho, 2021/09/17
- [PATCH v3 6/9] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device, Tong Ho, 2021/09/17
- [PATCH v3 8/9] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device, Tong Ho, 2021/09/17
- [PATCH v3 3/9] hw/nvram: Introduce Xilinx ZynqMP eFuse device, Tong Ho, 2021/09/17
- [PATCH v3 9/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage, Tong Ho, 2021/09/17
- [PATCH v3 7/9] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device,
Tong Ho <=
- [PATCH v3 1/9] hw/nvram: Introduce Xilinx eFuse QOM, Tong Ho, 2021/09/17
- [PATCH v3 4/9] hw/nvram: Introduce Xilinx battery-backed ram, Tong Ho, 2021/09/17
- Re: [PATCH v3 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM, Peter Maydell, 2021/09/27