[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 05/12] target/arm: Optimize MVE arithmetic ops
From: |
Peter Maydell |
Subject: |
[PATCH v2 05/12] target/arm: Optimize MVE arithmetic ops |
Date: |
Mon, 13 Sep 2021 10:54:33 +0100 |
Optimize MVE arithmetic ops when we have a TCG
vector operation we can use.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-mve.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 77b9f0db334..255cb860fec 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -838,7 +838,7 @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a)
return do_2op(s, a, gen_helper_mve_vpsel);
}
-#define DO_2OP(INSN, FN) \
+#define DO_2OP_VEC(INSN, FN, VECFN) \
static bool trans_##INSN(DisasContext *s, arg_2op *a) \
{ \
static MVEGenTwoOpFn * const fns[] = { \
@@ -847,20 +847,22 @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a)
gen_helper_mve_##FN##w, \
NULL, \
}; \
- return do_2op(s, a, fns[a->size]); \
+ return do_2op_vec(s, a, fns[a->size], VECFN); \
}
-DO_2OP(VADD, vadd)
-DO_2OP(VSUB, vsub)
-DO_2OP(VMUL, vmul)
+#define DO_2OP(INSN, FN) DO_2OP_VEC(INSN, FN, NULL)
+
+DO_2OP_VEC(VADD, vadd, tcg_gen_gvec_add)
+DO_2OP_VEC(VSUB, vsub, tcg_gen_gvec_sub)
+DO_2OP_VEC(VMUL, vmul, tcg_gen_gvec_mul)
DO_2OP(VMULH_S, vmulhs)
DO_2OP(VMULH_U, vmulhu)
DO_2OP(VRMULH_S, vrmulhs)
DO_2OP(VRMULH_U, vrmulhu)
-DO_2OP(VMAX_S, vmaxs)
-DO_2OP(VMAX_U, vmaxu)
-DO_2OP(VMIN_S, vmins)
-DO_2OP(VMIN_U, vminu)
+DO_2OP_VEC(VMAX_S, vmaxs, tcg_gen_gvec_smax)
+DO_2OP_VEC(VMAX_U, vmaxu, tcg_gen_gvec_umax)
+DO_2OP_VEC(VMIN_S, vmins, tcg_gen_gvec_smin)
+DO_2OP_VEC(VMIN_U, vminu, tcg_gen_gvec_umin)
DO_2OP(VABD_S, vabds)
DO_2OP(VABD_U, vabdu)
DO_2OP(VHADD_S, vhadds)
--
2.20.1
- [PATCH v2 02/12] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration, (continued)
- [PATCH v2 02/12] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration, Peter Maydell, 2021/09/13
- [PATCH v2 06/12] target/arm: Optimize MVE VNEG, VABS, Peter Maydell, 2021/09/13
- [PATCH v2 03/12] target/arm: Add TB flag for "MVE insns not predicated", Peter Maydell, 2021/09/13
- [PATCH v2 04/12] target/arm: Optimize MVE logic ops, Peter Maydell, 2021/09/13
- [PATCH v2 07/12] target/arm: Optimize MVE VDUP, Peter Maydell, 2021/09/13
- [PATCH v2 08/12] target/arm: Optimize MVE VMVN, Peter Maydell, 2021/09/13
- [PATCH v2 05/12] target/arm: Optimize MVE arithmetic ops,
Peter Maydell <=
- [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms, Peter Maydell, 2021/09/13
- Re: [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms, Richard Henderson, 2021/09/13
- Re: [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms, Peter Maydell, 2021/09/13
- Re: [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms, Richard Henderson, 2021/09/13
- Re: [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms, Peter Maydell, 2021/09/16
- Re: [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms, Richard Henderson, 2021/09/16
[PATCH v2 11/12] target/arm: Optimize MVE VSLI and VSRI, Peter Maydell, 2021/09/13
[PATCH v2 12/12] target/arm: Optimize MVE 1op-immediate insns, Peter Maydell, 2021/09/13