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[PULL 12/14] hw/arm/aspeed: Initialize AST2600 UART clock selection regi
From: |
Cédric Le Goater |
Subject: |
[PULL 12/14] hw/arm/aspeed: Initialize AST2600 UART clock selection registers |
Date: |
Fri, 3 Sep 2021 21:41:06 +0200 |
From: Peter Delevoryas <pdel@fb.com>
UART5 is typically used as the default debug UART on the AST2600, but
UART1 is also designed to be a debug UART. All the AST2600 UART's have
semi-configurable clock rates through registers in the System Control
Unit (SCU), but only UART5 works out of the box with zero-initialized
values. The rest of the UART's expect a few of the registers to be
initialized to non-zero values, or else the clock rate calculation will
yield zero or undefined (due to a divide-by-zero).
For reference, the U-Boot clock rate driver here shows the calculation:
https://github.com/facebook/openbmc-uboot/blob/main/drivers/clk/aspeed/clk_ast2600.c#L357)
To summarize, UART5 allows selection from 4 rates: 24 MHz, 192 MHz, 24 /
13 MHz, and 192 / 13 MHz. The other UART's allow selecting either the
"low" rate (UARTCLK) or the "high" rate (HUARTCLK). UARTCLK and HUARTCLK
are configurable themselves:
UARTCLK = UXCLK * R / (N * 2)
HUARTCLK = HUXCLK * HR / (HN * 2)
UXCLK and HUXCLK are also configurable, and depend on the APLL and/or
HPLL clock rates, which also derive from complicated calculations. Long
story short, there's lots of multiplication and division from
configurable registers, and most of these registers are zero-initialized
in QEMU, which at best is unexpected and at worst causes this clock rate
driver to hang from divide-by-zero's. This can also be difficult to
diagnose, because it may cause U-Boot to hang before serial console
initialization completes, requiring intervention from gdb.
This change just initializes all of these registers with default values
from the datasheet.
To test this, I used Facebook's AST2600 OpenBMC image for "fuji", with
the following diff applied (because fuji uses UART1 for console output,
not UART5).
@@ -323,8 +323,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev,
Error **errp)
}
/* UART - attach an 8250 to the IO space as our UART5 */
- serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
- aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
+ serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART1], 2,
+ aspeed_soc_get_irq(s, ASPEED_DEV_UART1),
38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
/* I2C */
Without these clock rate registers being initialized, U-Boot hangs in
the clock rate driver from a divide-by-zero, because the UART1 clock
rate register reads return zero, and there's no console output. After
initializing them with default values, fuji boots successfully.
git clone https://github.com/facebook/openbmc
cd openbmc
./sync_yocto.sh
source openbmc-init-build-env fuji build-fuji
bitbake fuji-image
cp ./tmp/deploy/images/fuji/flash-fuji /tmp/
dd if=/dev/zero of=/tmp/fixedsize-fuji bs=1M count=128
dd if=/tmp/flash-fuji of=/tmp/fixedsize-fuji bs=1k conv=notrunc
git clone --branch init-clock-sel-regs
https://github.com/peterdelevoryas/qemu
cd qemu
./configure --target-list=arm-softmmu --disable-vnc
make -j $(nproc)
./build/arm-softmmu/qemu-system-arm \
-machine ast2600-evb \
-drive file=/tmp/fixedsize-fuji,format=raw,if=mtd \
-serial stdio
Signed-off-by: Peter Delevoryas <pdel@fb.com>
[ clg: - reworked diff in commit log
- dropped CLK_SEL* changes which were already merged
- Subject update ]
Message-Id: <20210831142502.279485-1-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/aspeed_scu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 05edebedeb46..a95dca65f2f1 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -119,6 +119,8 @@
#define AST2600_CLK_SEL3 TO_REG(0x308)
#define AST2600_CLK_SEL4 TO_REG(0x310)
#define AST2600_CLK_SEL5 TO_REG(0x314)
+#define AST2600_UARTCLK_PARAM TO_REG(0x338)
+#define AST2600_HUARTCLK_PARAM TO_REG(0x33C)
#define AST2600_HW_STRAP1 TO_REG(0x500)
#define AST2600_HW_STRAP1_CLR TO_REG(0x504)
#define AST2600_HW_STRAP1_PROT TO_REG(0x508)
@@ -681,6 +683,8 @@ static const uint32_t
ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = {
[AST2600_CLK_SEL3] = 0x00000000,
[AST2600_CLK_SEL4] = 0xF3F40000,
[AST2600_CLK_SEL5] = 0x30000000,
+ [AST2600_UARTCLK_PARAM] = 0x00014506,
+ [AST2600_HUARTCLK_PARAM] = 0x000145C0,
[AST2600_CHIP_ID0] = 0x1234ABCD,
[AST2600_CHIP_ID1] = 0x88884444,
};
--
2.31.1
- [PULL 00/14] aspeed queue, Cédric Le Goater, 2021/09/03
- [PULL 13/14] hw/arm/aspeed: Allow machine to set UART default, Cédric Le Goater, 2021/09/03
- [PULL 14/14] hw/arm/aspeed: Add Fuji machine type, Cédric Le Goater, 2021/09/03
- [PULL 01/14] hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb, Cédric Le Goater, 2021/09/03
- [PULL 12/14] hw/arm/aspeed: Initialize AST2600 UART clock selection registers,
Cédric Le Goater <=
- [PULL 07/14] misc/pca9552: Fix LED status register indexing in pca955x_get_led(), Cédric Le Goater, 2021/09/03
- [PULL 05/14] hw: aspeed_gpio: Simplify 1.8V defines, Cédric Le Goater, 2021/09/03
- [PULL 08/14] arm/aspeed: rainier: Add i2c eeproms and muxes, Cédric Le Goater, 2021/09/03
- [PULL 10/14] hw/misc: Add Infineon DPS310 sensor model, Cédric Le Goater, 2021/09/03
- [PULL 11/14] arm/aspeed: Add DPS310 to Witherspoon and Rainier, Cédric Le Goater, 2021/09/03
- [PULL 09/14] aspeed: Emulate the AST2600A3, Cédric Le Goater, 2021/09/03
- [PULL 02/14] hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220a, Cédric Le Goater, 2021/09/03
- [PULL 04/14] watchdog: aspeed: Fix sequential control writes, Cédric Le Goater, 2021/09/03
- [PULL 06/14] hw: aspeed_gpio: Clarify GPIO controller name, Cédric Le Goater, 2021/09/03
- [PULL 03/14] watchdog: aspeed: Sanitize control register values, Cédric Le Goater, 2021/09/03