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[PATCH v2 7/9] escc: remove register changes from escc_reset_chn()
From: |
Mark Cave-Ayland |
Subject: |
[PATCH v2 7/9] escc: remove register changes from escc_reset_chn() |
Date: |
Thu, 2 Sep 2021 11:22:03 +0100 |
Now that register values at reset are handled elsewhere for all of device reset,
soft reset and hard reset, escc_reset_chn() only needs to handle initialisation
of internal device state.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/char/escc.c | 25 -------------------------
1 file changed, 25 deletions(-)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 1d90e77db7..c6b477ef78 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -142,7 +142,6 @@
#define MISC2_PLLCMD0 0x20
#define MISC2_PLLCMD1 0x40
#define MISC2_PLLCMD2 0x80
-#define MISC2_PLLDIS 0x30
#define W_EXTINT 15
#define EXTINT_DCD 0x08
#define EXTINT_SYNCINT 0x10
@@ -282,31 +281,7 @@ static void escc_update_irq(ESCCChannelState *s)
static void escc_reset_chn(ESCCChannelState *s)
{
- int i;
-
s->reg = 0;
- for (i = 0; i < ESCC_SERIAL_REGS; i++) {
- s->rregs[i] = 0;
- s->wregs[i] = 0;
- }
- /* 1X divisor, 1 stop bit, no parity */
- s->wregs[W_TXCTRL1] = TXCTRL1_1STOP;
- s->wregs[W_MINTR] = MINTR_RST_ALL;
- /* Synch mode tx clock = TRxC */
- s->wregs[W_CLOCK] = CLOCK_TRXC;
- /* PLL disabled */
- s->wregs[W_MISC2] = MISC2_PLLDIS;
- /* Enable most interrupts */
- s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
- EXTINT_TXUNDRN | EXTINT_BRKINT;
- if (s->disabled) {
- s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
- STATUS_CTS | STATUS_TXUNDRN;
- } else {
- s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
- }
- s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
-
s->rx = s->tx = 0;
s->rxint = s->txint = 0;
s->rxint_under_svc = s->txint_under_svc = 0;
--
2.20.1
- [PATCH v2 1/9] escc: checkpatch fixes, (continued)
[PATCH v2 5/9] escc: implement soft reset as described in the datasheet, Mark Cave-Ayland, 2021/09/02
[PATCH v2 6/9] escc: implement hard reset as described in the datasheet, Mark Cave-Ayland, 2021/09/02
[PATCH v2 7/9] escc: remove register changes from escc_reset_chn(),
Mark Cave-Ayland <=
[PATCH v2 8/9] escc: re-use escc_reset_chn() for hard and soft reset, Mark Cave-Ayland, 2021/09/02
[PATCH v2 9/9] escc: fix STATUS_SYNC bit in R_STATUS register, Mark Cave-Ayland, 2021/09/02