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[PULL 22/33] target/riscv: Use extracts for sraiw and srliw
From: |
Alistair Francis |
Subject: |
[PULL 22/33] target/riscv: Use extracts for sraiw and srliw |
Date: |
Wed, 1 Sep 2021 12:09:47 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
These operations can be done in one instruction on some hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvi.c.inc | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index e4726e618c..9e8d99be51 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -347,18 +347,28 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
}
+static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
+{
+ tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
+}
+
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
+}
+
+static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
+{
+ tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
--
2.31.1
- [PULL 15/33] target/riscv: Add DisasExtend to gen_arith*, (continued)
- [PULL 15/33] target/riscv: Add DisasExtend to gen_arith*, Alistair Francis, 2021/08/31
- [PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Alistair Francis, 2021/08/31
- [PULL 16/33] target/riscv: Remove gen_arith_div*, Alistair Francis, 2021/08/31
- [PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu, Alistair Francis, 2021/08/31
- [PULL 14/33] target/riscv: Introduce DisasExtend and new helpers, Alistair Francis, 2021/08/31
- [PULL 18/33] target/riscv: Move gen_* helpers for RVM, Alistair Francis, 2021/08/31
- [PULL 19/33] target/riscv: Move gen_* helpers for RVB, Alistair Francis, 2021/08/31
- [PULL 20/33] target/riscv: Add DisasExtend to gen_unary, Alistair Francis, 2021/08/31
- [PULL 21/33] target/riscv: Use DisasExtend in shift operations, Alistair Francis, 2021/08/31
- [PULL 23/33] target/riscv: Use get_gpr in branches, Alistair Francis, 2021/08/31
- [PULL 22/33] target/riscv: Use extracts for sraiw and srliw,
Alistair Francis <=
- [PULL 25/33] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation, Alistair Francis, 2021/08/31
- [PULL 24/33] target/riscv: Use {get, dest}_gpr for integer load/store, Alistair Francis, 2021/08/31
- [PULL 26/33] target/riscv: Fix hgeie, hgeip, Alistair Francis, 2021/08/31
- [PULL 27/33] target/riscv: Reorg csr instructions, Alistair Francis, 2021/08/31
- [PULL 28/33] target/riscv: Use {get,dest}_gpr for RVA, Alistair Francis, 2021/08/31
- [PULL 29/33] target/riscv: Use gen_shift_imm_fn for slli_uw, Alistair Francis, 2021/08/31
- [PULL 30/33] target/riscv: Use {get,dest}_gpr for RVF, Alistair Francis, 2021/08/31
- [PULL 32/33] target/riscv: Tidy trans_rvh.c.inc, Alistair Francis, 2021/08/31
- [PULL 31/33] target/riscv: Use {get,dest}_gpr for RVD, Alistair Francis, 2021/08/31
- [PULL 33/33] target/riscv: Use {get,dest}_gpr for RVV, Alistair Francis, 2021/08/31