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[PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror
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From: |
Philipp Tomsich |
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Subject: |
[PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec |
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Date: |
Mon, 23 Aug 2021 18:40:37 +0200 |
The slli.uw instruction is defined as
X(rd) = (EXTZ(X(rs)[31..0]) << shamt);
This rewrites its implementation to directly match this, allowing
for the small optimisation of not emitting the zero-extension if
the immediate shift is greater than 32.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
(no changes since v1)
target/riscv/insn_trans/trans_rvb.c.inc | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index b134abd263..3419dcf1bb 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -308,17 +308,14 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw
*a)
return false;
}
- TCGv source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
-
+ TCGv source = tcg_temp_new();
+ gen_get_gpr(source, a->rs1);
if (a->shamt < 32) {
- tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
- } else {
- tcg_gen_shli_tl(source1, source1, a->shamt);
+ tcg_gen_ext32u_tl(source, source);
}
-
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
+ tcg_gen_shli_tl(source, source, a->shamt);
+ gen_set_gpr(a->rd, source);
+ tcg_temp_free(source);
return true;
}
--
2.25.1
- [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension, (continued)
- [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/08/23
- [PATCH v3 10/15] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/08/23
- [PATCH v3 12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/08/23
- [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/08/23
- [PATCH v3 08/15] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/08/23
- [PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec,
Philipp Tomsich <=
- [PATCH v3 09/15] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/08/23
- [PATCH v3 15/15] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/08/23
- [PATCH v3 11/15] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/08/23
- [PATCH v3 13/15] target/riscv: Remove RVB (replaced by Zb[abcs], Philipp Tomsich, 2021/08/23