[PULL 00/14] target-arm queue

[Peter Maydell]

arm pullreq for rc1. All minor bugfixes, except for the 
sve-default-vector-length
patches, which are somewhere between a bugfix and a new feature.

thanks
-- PMM

The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a:

  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into 
staging (2021-07-27 08:35:01 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20210727

for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749:

  hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/smmuv3: Check 31st bit to see if CD is valid
 * qemu-options.hx: Fix formatting of -machine memory-backend option
 * hw: aspeed_gpio: Fix memory size
 * hw/arm/nseries: Display hexadecimal value with '0x' prefix
 * Add sve-default-vector-length cpu property
 * docs: Update path that mentions deprecated.rst
 * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
 * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
 * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending 
interrupts
 * target/arm: Report M-profile alignment faults correctly to the guest
 * target/arm: Add missing 'return's after calling v7m_exception_taken()
 * target/arm: Enforce that M-profile SP low 2 bits are always zero

----------------------------------------------------------------
Joe Komlodi (1):
      hw/arm/smmuv3: Check 31st bit to see if CD is valid

Joel Stanley (1):
      hw: aspeed_gpio: Fix memory size

Mao Zhongyi (1):
      docs: Update path that mentions deprecated.rst

Peter Maydell (7):
      qemu-options.hx: Fix formatting of -machine memory-backend option
      target/arm: Enforce that M-profile SP low 2 bits are always zero
      target/arm: Add missing 'return's after calling v7m_exception_taken()
      target/arm: Report M-profile alignment faults correctly to the guest
      hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending 
interrupts
      hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
      hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS

Philippe Mathieu-Daudé (1):
      hw/arm/nseries: Display hexadecimal value with '0x' prefix

Richard Henderson (3):
      target/arm: Correctly bound length in sve_zcr_get_valid_len
      target/arm: Export aarch64_sve_zcr_get_valid_len
      target/arm: Add sve-default-vector-length cpu property

 docs/system/arm/cpu-features.rst | 15 ++++++++++
 configure                        |  2 +-
 hw/arm/smmuv3-internal.h         |  2 +-
 target/arm/cpu.h                 |  5 ++++
 target/arm/internals.h           | 10 +++++++
 hw/arm/nseries.c                 |  2 +-
 hw/gpio/aspeed_gpio.c            |  3 +-
 hw/intc/armv7m_nvic.c            | 40 +++++++++++++++++++--------
 target/arm/cpu.c                 | 14 ++++++++--
 target/arm/cpu64.c               | 60 ++++++++++++++++++++++++++++++++++++++++
 target/arm/gdbstub.c             |  4 +++
 target/arm/helper.c              |  8 ++++--
 target/arm/m_helper.c            | 24 ++++++++++++----
 target/arm/translate.c           |  3 ++
 target/i386/cpu.c                |  2 +-
 MAINTAINERS                      |  2 +-
 qemu-options.hx                  | 30 +++++++++++---------
 17 files changed, 183 insertions(+), 43 deletions(-)