Re: [PATCH v2 10/22] target/loongarch: Add fixed point load/store instruction translation

[Richard Henderson]

On 7/20/21 11:53 PM, Song Gao wrote:
> This patch implement fixed point load/store instruction translation.
>
> This includes:
> - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
> - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
> - LDPTR.{W/D}, STPTR.{W/D}
> - PRELD
> - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
> - DBAR, IBAR
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/helper.h     |   3 +
>   target/loongarch/insns.decode |  58 ++++
>   target/loongarch/op_helper.c  |  15 +
>   target/loongarch/trans.inc.c  | 758 ++++++++++++++++++++++++++++++++++++++++++
>   target/loongarch/translate.c  |  29 ++
>   5 files changed, 863 insertions(+)
>
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index bbbcc26..5cd38c8 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -18,3 +18,6 @@ DEF_HELPER_2(bitrev_d, tl, env, tl)
>   
>   DEF_HELPER_FLAGS_1(loongarch_bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
>   DEF_HELPER_FLAGS_1(loongarch_dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
> +
> +DEF_HELPER_3(asrtle_d, void, env, tl, tl)
> +DEF_HELPER_3(asrtgt_d, void, env, tl, tl)
> diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
> index ec599a9..08fd232 100644
> --- a/target/loongarch/insns.decode
> +++ b/target/loongarch/insns.decode
> @@ -24,6 +24,9 @@
>   %lsbw    10:5
>   %msbd    16:6
>   %lsbd    10:6
> +%si14    10:s14
> +%hint    0:5
> +%whint   0:15
>   
>   #
>   # Argument sets
> @@ -40,6 +43,9 @@
>   &fmt_rdrjrksa3      rd rj rk sa3
>   &fmt_rdrjmsbwlsbw   rd rj msbw lsbw
>   &fmt_rdrjmsbdlsbd   rd rj msbd lsbd
> +&fmt_rdrjsi14       rd rj si14
> +&fmt_hintrjsi12     hint rj si12
> +&fmt_whint          whint
>   
>   #
>   # Formats
> @@ -56,6 +62,9 @@
>   @fmt_rdrjmsbwlsbw    .... ....... ..... . ..... ..... .....   
> &fmt_rdrjmsbwlsbw   %rd %rj %msbw %lsbw
>   @fmt_rdrjmsbdlsbd    .... ...... ...... ...... ..... .....    
> &fmt_rdrjmsbdlsbd   %rd %rj %msbd %lsbd
>   @fmt_rdrjrksa3       .... ........ .. ... ..... ..... .....   &fmt_rdrjrksa3  
>     %rd %rj %rk %sa3
> +@fmt_hintrjsi12      .... ...... ............ ..... .....     &fmt_hintrjsi12  
>    %hint %rj %si12
> +@fmt_whint           .... ........ ..... ...............      &fmt_whint       
>    %whint
> +@fmt_rdrjsi14        .... .... .............. ..... .....     &fmt_rdrjsi14    
>    %rd %rj %si14
>   
>   #
>   # Fixed point arithmetic operation instruction
> @@ -158,3 +167,52 @@ bstrins_w        0000 0000011 ..... 0 ..... ..... .....   
> @fmt_rdrjmsbwlsbw
>   bstrpick_w       0000 0000011 ..... 1 ..... ..... .....   @fmt_rdrjmsbwlsbw
>   bstrins_d        0000 000010 ...... ...... ..... .....    @fmt_rdrjmsbdlsbd
>   bstrpick_d       0000 000011 ...... ...... ..... .....    @fmt_rdrjmsbdlsbd
> +
> +#
> +# Fixed point load/store instruction
> +#
> +ld_b             0010 100000 ............ ..... .....     @fmt_rdrjsi12
> +ld_h             0010 100001 ............ ..... .....     @fmt_rdrjsi12
> +ld_w             0010 100010 ............ ..... .....     @fmt_rdrjsi12
> +ld_d             0010 100011 ............ ..... .....     @fmt_rdrjsi12
> +st_b             0010 100100 ............ ..... .....     @fmt_rdrjsi12
> +st_h             0010 100101 ............ ..... .....     @fmt_rdrjsi12
> +st_w             0010 100110 ............ ..... .....     @fmt_rdrjsi12
> +st_d             0010 100111 ............ ..... .....     @fmt_rdrjsi12
> +ld_bu            0010 101000 ............ ..... .....     @fmt_rdrjsi12
> +ld_hu            0010 101001 ............ ..... .....     @fmt_rdrjsi12
> +ld_wu            0010 101010 ............ ..... .....     @fmt_rdrjsi12
> +ldx_b            0011 10000000 00000 ..... ..... .....    @fmt_rdrjrk
> +ldx_h            0011 10000000 01000 ..... ..... .....    @fmt_rdrjrk
> +ldx_w            0011 10000000 10000 ..... ..... .....    @fmt_rdrjrk
> +ldx_d            0011 10000000 11000 ..... ..... .....    @fmt_rdrjrk
> +stx_b            0011 10000001 00000 ..... ..... .....    @fmt_rdrjrk
> +stx_h            0011 10000001 01000 ..... ..... .....    @fmt_rdrjrk
> +stx_w            0011 10000001 10000 ..... ..... .....    @fmt_rdrjrk
> +stx_d            0011 10000001 11000 ..... ..... .....    @fmt_rdrjrk
> +ldx_bu           0011 10000010 00000 ..... ..... .....    @fmt_rdrjrk
> +ldx_hu           0011 10000010 01000 ..... ..... .....    @fmt_rdrjrk
> +ldx_wu           0011 10000010 10000 ..... ..... .....    @fmt_rdrjrk
> +preld            0010 101011 ............ ..... .....     @fmt_hintrjsi12
> +dbar             0011 10000111 00100 ...............      @fmt_whint
> +ibar             0011 10000111 00101 ...............      @fmt_whint
> +ldptr_w          0010 0100 .............. ..... .....     @fmt_rdrjsi14
> +stptr_w          0010 0101 .............. ..... .....     @fmt_rdrjsi14
> +ldptr_d          0010 0110 .............. ..... .....     @fmt_rdrjsi14
> +stptr_d          0010 0111 .............. ..... .....     @fmt_rdrjsi14
> +ldgt_b           0011 10000111 10000 ..... ..... .....    @fmt_rdrjrk
> +ldgt_h           0011 10000111 10001 ..... ..... .....    @fmt_rdrjrk
> +ldgt_w           0011 10000111 10010 ..... ..... .....    @fmt_rdrjrk
> +ldgt_d           0011 10000111 10011 ..... ..... .....    @fmt_rdrjrk
> +ldle_b           0011 10000111 10100 ..... ..... .....    @fmt_rdrjrk
> +ldle_h           0011 10000111 10101 ..... ..... .....    @fmt_rdrjrk
> +ldle_w           0011 10000111 10110 ..... ..... .....    @fmt_rdrjrk
> +ldle_d           0011 10000111 10111 ..... ..... .....    @fmt_rdrjrk
> +stgt_b           0011 10000111 11000 ..... ..... .....    @fmt_rdrjrk
> +stgt_h           0011 10000111 11001 ..... ..... .....    @fmt_rdrjrk
> +stgt_w           0011 10000111 11010 ..... ..... .....    @fmt_rdrjrk
> +stgt_d           0011 10000111 11011 ..... ..... .....    @fmt_rdrjrk
> +stle_b           0011 10000111 11100 ..... ..... .....    @fmt_rdrjrk
> +stle_h           0011 10000111 11101 ..... ..... .....    @fmt_rdrjrk
> +stle_w           0011 10000111 11110 ..... ..... .....    @fmt_rdrjrk
> +stle_d           0011 10000111 11111 ..... ..... .....    @fmt_rdrjrk
> diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
> index 07c3d52..738e067 100644
> --- a/target/loongarch/op_helper.c
> +++ b/target/loongarch/op_helper.c
> @@ -144,3 +144,18 @@ target_ulong helper_loongarch_bitswap(target_ulong rt)
>   {
>       return (int32_t)bitswap(rt);
>   }
> +
> +/* loongarch assert op */
> +void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
> +{
> +    if (rj > rk) {
> +        do_raise_exception(env, EXCP_ADE, GETPC());
> +    }
> +}
> +
> +void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
> +{
> +    if (rj <= rk) {
> +        do_raise_exception(env, EXCP_ADE, GETPC());
> +    }
> +}
> diff --git a/target/loongarch/trans.inc.c b/target/loongarch/trans.inc.c
> index 8c5ba63..e38001b 100644
> --- a/target/loongarch/trans.inc.c
> +++ b/target/loongarch/trans.inc.c
> @@ -2116,3 +2116,761 @@ static bool trans_bstrpick_w(DisasContext *ctx, 
> arg_bstrpick_w *a)
>   
>       return true;
>   }
> +
> +/* Fixed point load/store instruction translation */
> +static bool trans_ld_b(DisasContext *ctx, arg_ld_b *a)
> +{
> +    TCGv t0;
> +    TCGv Rd = cpu_gpr[a->rd];
> +    int mem_idx = ctx->mem_idx;
> +
> +    if (a->rd == 0) {
> +        /* Nop */
> +        return true;
> +    }

A load into the zero register is not a nop.  It is a load with the result discarded.  One 
should still fault if the load is to an invalid address.

You should be using a common routine, passing in the MO_* operand.

> +#define ASRTGT                                \
> +    do {                                      \
> +        TCGv t1 = get_gpr(a->rj);             \
> +        TCGv t2 = get_gpr(a->rk);             \
> +        gen_helper_asrtgt_d(cpu_env, t1, t2); \
> +    } while (0)
> +
> +#define ASRTLE                                \
> +    do {                                      \
> +        TCGv t1 = get_gpr(a->rj);             \
> +        TCGv t2 = get_gpr(a->rk);             \
> +        gen_helper_asrtle_d(cpu_env, t1, t2); \
> +    } while (0)
> +
> +#define DECL_ARG(name)   \
> +    arg_ ## name arg = { \
> +        .rd = a->rd,     \
> +        .rj = a->rj,     \
> +        .rk = a->rk,     \
> +    };
> +
> +static bool trans_ldgt_b(DisasContext *ctx, arg_ldgt_b *a)
> +{
> +    ASRTGT;
> +    DECL_ARG(ldx_b)
> +    trans_ldx_b(ctx, &arg);
> +    return true;
> +}

Use of a common routine would avoid the macro ugliness.


r~