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[PULL 31/63] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32
From: |
Richard Henderson |
Subject: |
[PULL 31/63] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32 |
Date: |
Tue, 29 Jun 2021 11:54:23 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Implement tcg_gen_vec_shl{shr}{sar}16i_tl by adding corresponging i32 OP.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20210624105023.3852-4-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-gvec.h | 10 ++++++++++
tcg/tcg-op-gvec.c | 28 ++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index 2d5ad6ce12..e3c9f45926 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -408,16 +408,26 @@ void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a,
TCGv_i32 b);
void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
+void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
+void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
+void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
+
#if TARGET_LONG_BITS == 64
#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i64
#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64
#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64
#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64
+#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i64
+#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i64
+#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i64
#else
#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32
#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32
#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32
#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32
+#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i32
+#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i32
+#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i32
#endif
#endif
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 6d9a0aed62..c8fb403957 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -2678,6 +2678,13 @@ void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a,
int64_t c)
tcg_gen_andi_i64(d, d, mask);
}
+void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
+{
+ uint32_t mask = dup_const(MO_16, 0xffff << c);
+ tcg_gen_shli_i32(d, a, c);
+ tcg_gen_andi_i32(d, d, mask);
+}
+
void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz)
{
@@ -2729,6 +2736,13 @@ void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a,
int64_t c)
tcg_gen_andi_i64(d, d, mask);
}
+void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
+{
+ uint32_t mask = dup_const(MO_16, 0xffff >> c);
+ tcg_gen_shri_i32(d, a, c);
+ tcg_gen_andi_i32(d, d, mask);
+}
+
void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz)
{
@@ -2794,6 +2808,20 @@ void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a,
int64_t c)
tcg_temp_free_i64(s);
}
+void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
+{
+ uint32_t s_mask = dup_const(MO_16, 0x8000 >> c);
+ uint32_t c_mask = dup_const(MO_16, 0xffff >> c);
+ TCGv_i32 s = tcg_temp_new_i32();
+
+ tcg_gen_shri_i32(d, a, c);
+ tcg_gen_andi_i32(s, d, s_mask); /* isolate (shifted) sign bit */
+ tcg_gen_andi_i32(d, d, c_mask); /* clear out bits above sign */
+ tcg_gen_muli_i32(s, s, (2 << c) - 2); /* replicate isolated signs */
+ tcg_gen_or_i32(d, d, s); /* include sign extension */
+ tcg_temp_free_i32(s);
+}
+
void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz)
{
--
2.25.1
- [PULL 20/63] target/cris: Mark static arrays const, (continued)
- [PULL 20/63] target/cris: Mark static arrays const, Richard Henderson, 2021/06/29
- [PULL 27/63] target/cris: Remove dc->flagx_known, Richard Henderson, 2021/06/29
- [PULL 26/63] target/cris: Improve JMP_INDIRECT, Richard Henderson, 2021/06/29
- [PULL 23/63] target/cris: Add DISAS_UPDATE_NEXT, Richard Henderson, 2021/06/29
- [PULL 21/63] target/cris: Fold unhandled X_FLAG changes into cpustate_changed, Richard Henderson, 2021/06/29
- [PULL 24/63] target/cris: Add DISAS_DBRANCH, Richard Henderson, 2021/06/29
- [PULL 10/63] target/avr: Add DisasContextBase to DisasContext, Richard Henderson, 2021/06/29
- [PULL 14/63] target/cris: Remove DISAS_SWI, Richard Henderson, 2021/06/29
- [PULL 30/63] tcg: Add tcg_gen_vec_add{sub}8_i32, Richard Henderson, 2021/06/29
- [PULL 25/63] target/cris: Use tcg_gen_lookup_and_goto_ptr, Richard Henderson, 2021/06/29
- [PULL 31/63] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32,
Richard Henderson <=
- [PULL 32/63] tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32, Richard Henderson, 2021/06/29
- [PULL 28/63] target/cris: Do not exit tb for X_FLAG changes, Richard Henderson, 2021/06/29
- [PULL 35/63] tcg: Add flags argument to bswap opcodes, Richard Henderson, 2021/06/29
- [PULL 34/63] tcg: Use correct trap number for page faults on *BSD systems, Richard Henderson, 2021/06/29
- [PULL 16/63] target/cris: Mark exceptions as DISAS_NORETURN, Richard Henderson, 2021/06/29
- [PULL 36/63] tcg/i386: Support bswap flags, Richard Henderson, 2021/06/29
- [PULL 38/63] tcg/aarch64: Support bswap flags, Richard Henderson, 2021/06/29
- [PULL 39/63] tcg/arm: Support bswap flags, Richard Henderson, 2021/06/29
- [PULL 33/63] tcg: Implement tcg_gen_vec_add{sub}32_tl, Richard Henderson, 2021/06/29
- [PULL 37/63] tcg/aarch64: Merge tcg_out_rev{16,32,64}, Richard Henderson, 2021/06/29