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[PULL 2/4] Hexagon (target/hexagon) fix l2fetch instructions
From: |
Taylor Simpson |
Subject: |
[PULL 2/4] Hexagon (target/hexagon) fix l2fetch instructions |
Date: |
Fri, 18 Jun 2021 14:06:40 -0500 |
Y4_l2fetch == l2fetch(Rs32, Rt32)
Y5_l2fetch == l2fetch(Rs32, Rtt32)
The semantics for these instructions are present, but the encodings
are missing.
Note that these are treated as nops in qemu, so we add overrides.
Test case added to tests/tcg/hexagon/misc.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1622589584-22571-3-git-send-email-tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 11 +++++++++++
tests/tcg/hexagon/misc.c | 9 +++++++++
target/hexagon/imported/encode_pp.def | 3 +++
3 files changed, 23 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 18fcdbc..a375d6a 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -734,4 +734,15 @@
#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
+/* Nothing to do for these in qemu, need to suppress compiler warnings */
+#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
+ do { \
+ RsV = RsV; \
+ RtV = RtV; \
+ } while (0)
+#define fGEN_TCG_Y5_l2fetch(SHORTCODE) \
+ do { \
+ RsV = RsV; \
+ } while (0)
+
#endif
diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c
index 9e139f3..f0b1947 100644
--- a/tests/tcg/hexagon/misc.c
+++ b/tests/tcg/hexagon/misc.c
@@ -326,6 +326,13 @@ void test_lsbnew(void)
check(result, 5);
}
+void test_l2fetch(void)
+{
+ /* These don't do anything in qemu, just make sure they don't assert */
+ asm volatile ("l2fetch(r0, r1)\n\t"
+ "l2fetch(r0, r3:2)\n\t");
+}
+
int main()
{
int res;
@@ -459,6 +466,8 @@ int main()
test_lsbnew();
+ test_l2fetch();
+
puts(err ? "FAIL" : "PASS");
return err;
}
diff --git a/target/hexagon/imported/encode_pp.def
b/target/hexagon/imported/encode_pp.def
index 35ae3d2..939c6fc 100644
--- a/target/hexagon/imported/encode_pp.def
+++ b/target/hexagon/imported/encode_pp.def
@@ -493,6 +493,9 @@ DEF_ENC32(Y2_dccleana, ICLASS_ST" 000 00 00sssss
PP------ --------")
DEF_ENC32(Y2_dcinva, ICLASS_ST" 000 00 01sssss PP------ --------")
DEF_ENC32(Y2_dccleaninva, ICLASS_ST" 000 00 10sssss PP------ --------")
+DEF_ENC32(Y4_l2fetch, ICLASS_ST" 011 00 00sssss PP-ttttt 000-----")
+DEF_ENC32(Y5_l2fetch, ICLASS_ST" 011 01 00sssss PP-ttttt --------")
+
/*******************************/
/* */
/* */
--
2.7.4
- [PULL 0/4] Hexagon (target/hexagon) bug fixes, Taylor Simpson, 2021/06/18
- [PULL 3/4] Hexagon (target/hexagon) cleanup gen_store_conditional[48] functions, Taylor Simpson, 2021/06/18
- [PULL 2/4] Hexagon (target/hexagon) fix l2fetch instructions,
Taylor Simpson <=
- [PULL 4/4] Hexagon (target/hexagon) remove unused TCG variables, Taylor Simpson, 2021/06/18
- [PULL 1/4] Hexagon (target/hexagon) fix bug in fLSBNEW*, Taylor Simpson, 2021/06/18
- RE: [PULL 0/4] Hexagon (target/hexagon) bug fixes, Taylor Simpson, 2021/06/23
- Re: [PULL 0/4] Hexagon (target/hexagon) bug fixes, Peter Maydell, 2021/06/29
- Re: [PULL 0/4] Hexagon (target/hexagon) bug fixes, Peter Maydell, 2021/06/29