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[PULL 32/32] target/riscv: rvb: add b-ext version cpu option
From: |
Alistair Francis |
Subject: |
[PULL 32/32] target/riscv: rvb: add b-ext version cpu option |
Date: |
Tue, 8 Jun 2021 10:29:47 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Default b-ext version is v0.93.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 +++
target/riscv/cpu.c | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de9262c930..bf1c899c00 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -83,6 +83,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
+#define BEXT_VERSION_0_93_0 0x00009300
#define VEXT_VERSION_0_07_1 0x00000701
enum {
@@ -132,6 +133,7 @@ struct CPURISCVState {
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
+ target_ulong bext_ver;
target_ulong vext_ver;
target_ulong misa;
target_ulong misa_mask;
@@ -297,6 +299,7 @@ struct RISCVCPU {
char *priv_spec;
char *user_spec;
+ char *bext_spec;
char *vext_spec;
uint16_t vlen;
uint16_t elen;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5702c53c62..991a6bb760 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -127,6 +127,11 @@ static void set_priv_version(CPURISCVState *env, int
priv_ver)
env->priv_ver = priv_ver;
}
+static void set_bext_version(CPURISCVState *env, int bext_ver)
+{
+ env->bext_ver = bext_ver;
+}
+
static void set_vext_version(CPURISCVState *env, int vext_ver)
{
env->vext_ver = vext_ver;
@@ -388,6 +393,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
+ int bext_version = BEXT_VERSION_0_93_0;
int vext_version = VEXT_VERSION_0_07_1;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -412,6 +418,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_priv_version(env, priv_version);
+ set_bext_version(env, bext_version);
set_vext_version(env, vext_version);
if (cpu->cfg.mmu) {
@@ -491,6 +498,21 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
if (cpu->cfg.ext_b) {
target_misa |= RVB;
+
+ if (cpu->cfg.bext_spec) {
+ if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
+ bext_version = BEXT_VERSION_0_93_0;
+ } else {
+ error_setg(errp,
+ "Unsupported bitmanip spec version '%s'",
+ cpu->cfg.bext_spec);
+ return;
+ }
+ } else {
+ qemu_log("bitmanip version is not specified, "
+ "use the default value v0.93\n");
+ }
+ set_bext_version(env, bext_version);
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
@@ -569,6 +591,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+ DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
--
2.31.1
- [PULL 22/32] target/riscv: rvb: sign-extend instructions, (continued)
- [PULL 22/32] target/riscv: rvb: sign-extend instructions, Alistair Francis, 2021/06/07
- [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, Alistair Francis, 2021/06/07
- [PULL 24/32] target/riscv: rvb: single-bit instructions, Alistair Francis, 2021/06/07
- [PULL 25/32] target/riscv: rvb: shift ones, Alistair Francis, 2021/06/07
- [PULL 26/32] target/riscv: rvb: rotate (left/right), Alistair Francis, 2021/06/07
- [PULL 27/32] target/riscv: rvb: generalized reverse, Alistair Francis, 2021/06/07
- [PULL 28/32] target/riscv: rvb: generalized or-combine, Alistair Francis, 2021/06/07
- [PULL 29/32] target/riscv: rvb: address calculation, Alistair Francis, 2021/06/07
- [PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend, Alistair Francis, 2021/06/07
- [PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line, Alistair Francis, 2021/06/07
- [PULL 32/32] target/riscv: rvb: add b-ext version cpu option,
Alistair Francis <=
- Re: [PULL 00/32] riscv-to-apply queue, Peter Maydell, 2021/06/08