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[PULL 091/114] target/arm: Implement SVE2 crypto destructive binary oper
From: |
Peter Maydell |
Subject: |
[PULL 091/114] target/arm: Implement SVE2 crypto destructive binary operations |
Date: |
Tue, 25 May 2021 16:03:01 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-70-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
target/arm/sve.decode | 7 +++++++
target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++
3 files changed, 50 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index dcdde85f866..e808e6ba408 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4256,6 +4256,11 @@ static inline bool isar_feature_aa64_sve2_bitperm(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
}
+static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
+}
+
static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a9cf3bea3e6..46ebb5e2f8b 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -118,6 +118,8 @@
@pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
&rrr_esz rn=%reg_movprfx
+@rdn_rm_e0 ........ .. ...... ...... rm:5 rd:5 \
+ &rrr_esz rn=%reg_movprfx esz=0
@rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
&rri_esz rn=%reg_movprfx imm=%sh8_i8u
@rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
@@ -1564,3 +1566,8 @@ STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
# SVE2 crypto unary operations
# AESMC and AESIMC
AESMC 01000101 00 10000011100 decrypt:1 00000 rd:5
+
+# SVE2 crypto destructive binary operations
+AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0
+AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0
+SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 79b49915492..3b977b24625 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -8159,3 +8159,41 @@ static bool trans_AESMC(DisasContext *s, arg_AESMC *a)
}
return true;
}
+
+static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
+{
+ if (!dc_isar_feature(aa64_sve2_aes, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
+ a->rd, a->rn, a->rm, decrypt);
+ }
+ return true;
+}
+
+static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
+{
+ return do_aese(s, a, false);
+}
+
+static bool trans_AESD(DisasContext *s, arg_rrr_esz *a)
+{
+ return do_aese(s, a, true);
+}
+
+static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
+ }
+ return true;
+}
+
+static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
+{
+ return do_sm4(s, a, gen_helper_crypto_sm4e);
+}
--
2.20.1
- [PULL 083/114] target/arm: Implement SVE2 integer multiply long (indexed), (continued)
- [PULL 083/114] target/arm: Implement SVE2 integer multiply long (indexed), Peter Maydell, 2021/05/25
- [PULL 085/114] target/arm: Implement SVE2 complex integer dot product, Peter Maydell, 2021/05/25
- [PULL 086/114] target/arm: Macroize helper_gvec_{s,u}dot_{b,h}, Peter Maydell, 2021/05/25
- [PULL 080/114] target/arm: Implement SVE2 signed saturating doubling multiply high, Peter Maydell, 2021/05/25
- [PULL 090/114] target/arm: Implement SVE2 crypto unary operations, Peter Maydell, 2021/05/25
- [PULL 073/114] target/arm: Split out formats for 2 vectors + 1 index, Peter Maydell, 2021/05/25
- [PULL 088/114] target/arm: Implement SVE mixed sign dot product (indexed), Peter Maydell, 2021/05/25
- [PULL 087/114] target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}, Peter Maydell, 2021/05/25
- [PULL 093/114] target/arm: Implement SVE2 TBL, TBX, Peter Maydell, 2021/05/25
- [PULL 089/114] target/arm: Implement SVE mixed sign dot product, Peter Maydell, 2021/05/25
- [PULL 091/114] target/arm: Implement SVE2 crypto destructive binary operations,
Peter Maydell <=
- [PULL 092/114] target/arm: Implement SVE2 crypto constructive binary operations, Peter Maydell, 2021/05/25
- [PULL 094/114] target/arm: Implement SVE2 FCVTNT, Peter Maydell, 2021/05/25
- [PULL 084/114] target/arm: Implement SVE2 complex integer multiply-add (indexed), Peter Maydell, 2021/05/25
- Re: [PULL 000/114] target-arm queue, Peter Maydell, 2021/05/25