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[PULL 026/114] target/arm: Implement SVE2 integer unary operations (pred
From: |
Peter Maydell |
Subject: |
[PULL 026/114] target/arm: Implement SVE2 integer unary operations (predicated) |
Date: |
Tue, 25 May 2021 16:01:56 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-sve.h | 13 +++++++++++
target/arm/sve.decode | 7 ++++++
target/arm/sve_helper.c | 21 +++++++++++++++++
target/arm/translate-sve.c | 47 ++++++++++++++++++++++++++++++++++++++
4 files changed, 88 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index b2a274b40b0..9992e93e2b8 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -502,6 +502,19 @@ DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr,
ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_rbit_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqabs_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqabs_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqabs_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqabs_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_sqneg_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqneg_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqneg_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sqneg_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_urecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_ursqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve_splice, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_b, TCG_CALL_NO_RWG,
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 0524c01fcff..5ba542969b4 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1105,3 +1105,10 @@ PMUL_zzz 00000100 00 1 ..... 0110 01 ..... .....
@rd_rn_rm_e0
SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn
UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn
+
+### SVE2 integer unary operations (predicated)
+
+URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn
+URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn
+SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn
+SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index f44b4138cc9..7a08c24f2dd 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -728,6 +728,27 @@ DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16)
DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32)
DO_ZPZ_D(sve_rbit_d, uint64_t, revbit64)
+#define DO_SQABS(X) \
+ ({ __typeof(X) x_ = (X), min_ = 1ull << (sizeof(X) * 8 - 1); \
+ x_ >= 0 ? x_ : x_ == min_ ? -min_ - 1 : -x_; })
+
+DO_ZPZ(sve2_sqabs_b, int8_t, H1, DO_SQABS)
+DO_ZPZ(sve2_sqabs_h, int16_t, H1_2, DO_SQABS)
+DO_ZPZ(sve2_sqabs_s, int32_t, H1_4, DO_SQABS)
+DO_ZPZ_D(sve2_sqabs_d, int64_t, DO_SQABS)
+
+#define DO_SQNEG(X) \
+ ({ __typeof(X) x_ = (X), min_ = 1ull << (sizeof(X) * 8 - 1); \
+ x_ == min_ ? -min_ - 1 : -x_; })
+
+DO_ZPZ(sve2_sqneg_b, uint8_t, H1, DO_SQNEG)
+DO_ZPZ(sve2_sqneg_h, uint16_t, H1_2, DO_SQNEG)
+DO_ZPZ(sve2_sqneg_s, uint32_t, H1_4, DO_SQNEG)
+DO_ZPZ_D(sve2_sqneg_d, uint64_t, DO_SQNEG)
+
+DO_ZPZ(sve2_urecpe_s, uint32_t, H1_4, helper_recpe_u32)
+DO_ZPZ(sve2_ursqrte_s, uint32_t, H1_4, helper_rsqrte_u32)
+
/* Three-operand expander, unpredicated, in which the third operand is "wide".
*/
#define DO_ZZW(NAME, TYPE, TYPEW, H, OP) \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 208d9ea7e07..c30b3c476e0 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5884,3 +5884,50 @@ static bool trans_UADALP_zpzz(DisasContext *s,
arg_rprr_esz *a)
}
return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
}
+
+/*
+ * SVE2 integer unary operations (predicated)
+ */
+
+static bool do_sve2_zpz_ool(DisasContext *s, arg_rpr_esz *a,
+ gen_helper_gvec_3 *fn)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_zpz_ool(s, a, fn);
+}
+
+static bool trans_URECPE(DisasContext *s, arg_rpr_esz *a)
+{
+ if (a->esz != 2) {
+ return false;
+ }
+ return do_sve2_zpz_ool(s, a, gen_helper_sve2_urecpe_s);
+}
+
+static bool trans_URSQRTE(DisasContext *s, arg_rpr_esz *a)
+{
+ if (a->esz != 2) {
+ return false;
+ }
+ return do_sve2_zpz_ool(s, a, gen_helper_sve2_ursqrte_s);
+}
+
+static bool trans_SQABS(DisasContext *s, arg_rpr_esz *a)
+{
+ static gen_helper_gvec_3 * const fns[4] = {
+ gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h,
+ gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d,
+ };
+ return do_sve2_zpz_ool(s, a, fns[a->esz]);
+}
+
+static bool trans_SQNEG(DisasContext *s, arg_rpr_esz *a)
+{
+ static gen_helper_gvec_3 * const fns[4] = {
+ gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h,
+ gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d,
+ };
+ return do_sve2_zpz_ool(s, a, fns[a->esz]);
+}
--
2.20.1
- [PULL 018/114] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1], (continued)
- [PULL 018/114] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1], Peter Maydell, 2021/05/25
- [PULL 014/114] accel/tcg: Add tlb_flush_range_by_mmuidx(), Peter Maydell, 2021/05/25
- [PULL 015/114] accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus(), Peter Maydell, 2021/05/25
- [PULL 020/114] target/arm: Add support for FEAT_TLBIOS, Peter Maydell, 2021/05/25
- [PULL 021/114] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type, Peter Maydell, 2021/05/25
- [PULL 019/114] target/arm: Add support for FEAT_TLBIRANGE, Peter Maydell, 2021/05/25
- [PULL 023/114] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2, Peter Maydell, 2021/05/25
- [PULL 024/114] target/arm: Implement SVE2 Integer Multiply - Unpredicated, Peter Maydell, 2021/05/25
- [PULL 022/114] disas/libvixl: Protect C system header for C++ compiler, Peter Maydell, 2021/05/25
- [PULL 025/114] target/arm: Implement SVE2 integer pairwise add and accumulate long, Peter Maydell, 2021/05/25
- [PULL 026/114] target/arm: Implement SVE2 integer unary operations (predicated),
Peter Maydell <=
- [PULL 028/114] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated), Peter Maydell, 2021/05/25
- [PULL 030/114] target/arm: Implement SVE2 integer pairwise arithmetic, Peter Maydell, 2021/05/25
- [PULL 031/114] target/arm: Implement SVE2 saturating add/subtract (predicated), Peter Maydell, 2021/05/25
- [PULL 029/114] target/arm: Implement SVE2 integer halving add/subtract (predicated), Peter Maydell, 2021/05/25
- [PULL 027/114] target/arm: Split out saturating/rounding shifts from neon, Peter Maydell, 2021/05/25
- [PULL 034/114] target/arm: Implement SVE2 integer add/subtract wide, Peter Maydell, 2021/05/25
- [PULL 040/114] target/arm: Implement SVE2 complex integer add, Peter Maydell, 2021/05/25
- [PULL 039/114] target/arm: Implement SVE2 bitwise permute, Peter Maydell, 2021/05/25
- [PULL 036/114] target/arm: Implement SVE2 PMULLB, PMULLT, Peter Maydell, 2021/05/25
- [PULL 047/114] target/arm: Implement SVE2 floating-point pairwise, Peter Maydell, 2021/05/25