---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 17 ++++
target/riscv/insn_trans/trans_rvp.c.inc | 16 ++++
target/riscv/packed_helper.c | 102 ++++++++++++++++++++++++
4 files changed, 144 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 20bf400ac2..0ecd4d53f9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1193,3 +1193,12 @@ DEF_HELPER_3(sll16, tl, env, tl, tl)
DEF_HELPER_3(ksll16, tl, env, tl, tl)
DEF_HELPER_3(kslra16, tl, env, tl, tl)
DEF_HELPER_3(kslra16_u, tl, env, tl, tl)
+
+DEF_HELPER_3(sra8, tl, env, tl, tl)
+DEF_HELPER_3(sra8_u, tl, env, tl, tl)
+DEF_HELPER_3(srl8, tl, env, tl, tl)
+DEF_HELPER_3(srl8_u, tl, env, tl, tl)
+DEF_HELPER_3(sll8, tl, env, tl, tl)
+DEF_HELPER_3(ksll8, tl, env, tl, tl)
+DEF_HELPER_3(kslra8, tl, env, tl, tl)
+DEF_HELPER_3(kslra8_u, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f053bfeb7..cc782fcde5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -24,6 +24,7 @@
%sh10 20:10
%sh4 20:4
+%sh3 20:3
%csr 20:12
%rm 12:3
%nf 29:3 !function=ex_plus_1
@@ -61,6 +62,7 @@
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1
%rd
@sh4 ...... ...... ..... ... ..... ....... &shift shamt=%sh4 %rs1
%rd
+@sh3 ...... ...... ..... ... ..... ....... &shift shamt=%sh3 %rs1
%rd
@csr ............ ..... ... ..... ....... %csr %rs1
%rd
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1
%rd
@@ -652,3 +654,18 @@ ksll16 0110010 ..... ..... 000 ..... 1111111 @r
kslli16 0111010 1.... ..... 000 ..... 1111111 @sh4
kslra16 0101011 ..... ..... 000 ..... 1111111 @r
kslra16_u 0110011 ..... ..... 000 ..... 1111111 @r
+
+sra8 0101100 ..... ..... 000 ..... 1111111 @r
+sra8_u 0110100 ..... ..... 000 ..... 1111111 @r
+srai8 0111100 00... ..... 000 ..... 1111111 @sh3
+srai8_u 0111100 01... ..... 000 ..... 1111111 @sh3
+srl8 0101101 ..... ..... 000 ..... 1111111 @r
+srl8_u 0110101 ..... ..... 000 ..... 1111111 @r
+srli8 0111101 00... ..... 000 ..... 1111111 @sh3
+srli8_u 0111101 01... ..... 000 ..... 1111111 @sh3
+sll8 0101110 ..... ..... 000 ..... 1111111 @r
+slli8 0111110 00... ..... 000 ..... 1111111 @sh3
+ksll8 0110110 ..... ..... 000 ..... 1111111 @r
+kslli8 0111110 01... ..... 000 ..... 1111111 @sh3
+kslra8 0101111 ..... ..... 000 ..... 1111111 @r
+kslra8_u 0110111 ..... ..... 000 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 848edab7e5..12a64849eb 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -353,3 +353,19 @@ GEN_RVP_SHIFTI(slli16, sll16, tcg_gen_vec_shl16i_i64);
GEN_RVP_SHIFTI(srai16_u, sra16_u, NULL);
GEN_RVP_SHIFTI(srli16_u, srl16_u, NULL);
GEN_RVP_SHIFTI(kslli16, ksll16, NULL);
+
+/* SIMD 8-bit Shift Instructions */
+GEN_RVP_SHIFT(sra8, tcg_gen_gvec_sars, 0);
+GEN_RVP_SHIFT(srl8, tcg_gen_gvec_shrs, 0);
+GEN_RVP_SHIFT(sll8, tcg_gen_gvec_shls, 0);
+GEN_RVP_R_OOL(sra8_u);
+GEN_RVP_R_OOL(srl8_u);
+GEN_RVP_R_OOL(ksll8);
+GEN_RVP_R_OOL(kslra8);
+GEN_RVP_R_OOL(kslra8_u);
+GEN_RVP_SHIFTI(srai8, sra8, tcg_gen_vec_sar8i_i64);
+GEN_RVP_SHIFTI(srli8, srl8, tcg_gen_vec_shr8i_i64);
+GEN_RVP_SHIFTI(slli8, sll8, tcg_gen_vec_shl8i_i64);
+GEN_RVP_SHIFTI(srai8_u, sra8_u, NULL);
+GEN_RVP_SHIFTI(srli8_u, srl8_u, NULL);
+GEN_RVP_SHIFTI(kslli8, ksll8, NULL);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 7e31c2fe46..ab9ebc472b 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -529,3 +529,105 @@ static inline void do_kslra16_u(CPURISCVState *env, void
*vd, void *va,
}
RVPR(kslra16_u, 1, 2);
+
+/* SIMD 8-bit Shift Instructions */
+static inline void do_sra8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x7;
+ d[i] = a[i] >> shift;
+}
+
+RVPR(sra8, 1, 1);
+
+static inline void do_srl8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint8_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x7;
+ d[i] = a[i] >> shift;
+}
+
+RVPR(srl8, 1, 1);
+
+static inline void do_sll8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint8_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x7;
+ d[i] = a[i] << shift;
+}
+
+RVPR(sll8, 1, 1);
+
+static inline void do_sra8_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x7;
+ d[i] = vssra8(env, 0, a[i], shift);
+}
+
+RVPR(sra8_u, 1, 1);
+
+static inline void do_srl8_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint8_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x7;
+ d[i] = vssrl8(env, 0, a[i], shift);
+}
+
+RVPR(srl8_u, 1, 1);
+
+static inline void do_ksll8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va, result;
+ uint8_t shift = *(uint8_t *)vb & 0x7;
+
+ result = a[i] << shift;
+ if (shift > (clrsb32(a[i]) - 24)) {
+ env->vxsat = 0x1;
+ d[i] = (a[i] & INT8_MIN) ? INT8_MIN : INT8_MAX;
+ } else {
+ d[i] = result;
+ }
+}
+
+RVPR(ksll8, 1, 1);
+
+static inline void do_kslra8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va;
+ int32_t shift = sextract32((*(uint32_t *)vb), 0, 4);
+
+ if (shift >= 0) {
+ do_ksll8(env, vd, va, vb, i);
+ } else {
+ shift = -shift;
+ shift = (shift == 8) ? 7 : shift;
+ d[i] = a[i] >> shift;
+ }
+}
+
+RVPR(kslra8, 1, 1);
+
+static inline void do_kslra8_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va;
+ int32_t shift = sextract32((*(uint32_t *)vb), 0, 4);
+
+ if (shift >= 0) {
+ do_ksll8(env, vd, va, vb, i);
+ } else {
+ shift = -shift;
+ shift = (shift == 8) ? 7 : shift;
+ d[i] = vssra8(env, 0, a[i], shift);
+ }
+}
+
+RVPR(kslra8_u, 1, 1);