Re: [PATCH v1 06/11] target/arm: Implement bfloat16 dot product (vector)

[Richard Henderson]

On 5/18/21 7:15 AM, Peter Maydell wrote:
> On Sat, 17 Apr 2021 at 01:02, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > This is BFDOT for both AArch64 AdvSIMD and SVE,
> > and VDOT.BF16 for AArch32 NEON.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>
> > @@ -12326,6 +12336,16 @@ static void 
> > disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
> >           }
> >           return;
> >
> > +    case 0xf: /* BFDOT */
> > +        switch (size) {
> > +        case 1:
> > +            gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, 
> > gen_helper_gvec_bfdot);
> > +            break;
> > +        default:
> > +            g_assert_not_reached();
> > +        }
> > +        return;
>
> The switch on size here seems unnecessary to me given we've already
> decoded size earlier in the function.

Size is opcode here, and the switch gains extra members as we continue.  I'm 
beginning the form we need to continue with.


r~