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[Bug 1922773] Re: RISCV32 illegal instruction exception


From: Thomas Huth
Subject: [Bug 1922773] Re: RISCV32 illegal instruction exception
Date: Sat, 15 May 2021 10:23:22 -0000

The QEMU project is currently moving its bug tracking to another system.
For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting the bug state to "Incomplete" now.

If the bug has already been fixed in the latest upstream version of QEMU,
then please close this ticket as "Fix released".

If it is not fixed yet and you think that this bug report here is still
valid, then you have two options:

1) If you already have an account on gitlab.com, please open a new ticket
for this problem in our new tracker here:

    https://gitlab.com/qemu-project/qemu/-/issues

and then close this ticket here on Launchpad (or let it expire auto-
matically after 60 days). Please mention the URL of this bug ticket on
Launchpad in the new ticket on GitLab.

2) If you don't have an account on gitlab.com and don't intend to get
one, but still would like to keep this ticket opened, then please switch
the state back to "New" or "Confirmed" within the next 60 days (other-
wise it will get closed as "Expired"). We will then eventually migrate
the ticket automatically to the new system (but you won't be the reporter
of the bug in the new system and thus you won't get notified on changes
anymore).

Thank you and sorry for the inconvenience.


** Changed in: qemu
       Status: New => Incomplete

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https://bugs.launchpad.net/bugs/1922773

Title:
  RISCV32 illegal instruction exception

Status in QEMU:
  Incomplete

Bug description:
  I'm running a machine learning model on qemu riscv32 and I ran into
  illegal instruction exception for some reason. I wasn't sure if this
  is a bug and if so whether it is related to zephyr or qemu, however
  I'll try to provide as much as information to get a better
  understanding.

  Here is the assembly code that I'm running:

  0x8000bd74 <+0>:      lw      a4,0(a0)
     0x8000bd76 <+2>:   lw      a5,8(a0)
     0x8000bd78 <+4>:   lw      a0,0(a4)
     0x8000bd7a <+6>:   lw      a1,0(a5)
     0x8000bd7c <+8>:   li      a3,0
     0x8000bd7e <+10>:  j       0x8000bda4 <fused_nn_pad_layout_transform+48>
     0x8000bd80 <+12>:  addi    a5,a3,-2
     0x8000bd84 <+16>:  li      a2,27
     0x8000bd86 <+18>:  bgeu    a2,a5,0x8000bdae 
<fused_nn_pad_layout_transform+58>
  => 0x8000bd8a <+22>:  fmv.w.x fa5,zero
     0x8000bd8e <+26>:  slli    a5,a3,0x5
     0x8000bd92 <+30>:  add     a5,a5,a4
     0x8000bd94 <+32>:  slli    a5,a5,0x2
     0x8000bd96 <+34>:  add     a5,a5,a1
     0x8000bd98 <+36>:  fsw     fa5,0(a5)
     0x8000bd9a <+38>:  addi    a4,a4,1
     0x8000bd9c <+40>:  li      a5,31
     0x8000bd9e <+42>:  bge     a5,a4,0x8000bd80 
<fused_nn_pad_layout_transform+12>
     0x8000bda2 <+46>:  addi    a3,a3,1
     0x8000bda4 <+48>:  li      a5,31
     0x8000bda6 <+50>:  blt     a5,a3,0x8000bde0 
<fused_nn_pad_layout_transform+108>
     0x8000bdaa <+54>:  li      a4,0
     0x8000bdac <+56>:  j       0x8000bd9c <fused_nn_pad_layout_transform+40>
     0x8000bdae <+58>:  li      a5,1
     0x8000bdb0 <+60>:  bge     a5,a4,0x8000bdd4 
<fused_nn_pad_layout_transform+96>
     0x8000bdb4 <+64>:  li      a5,29
     0x8000bdb6 <+66>:  blt     a5,a4,0x8000bdda 
<fused_nn_pad_layout_transform+102>
     0x8000bdba <+70>:  li      a5,28
     0x8000bdbc <+72>:  mul     a5,a3,a5
     0x8000bdc0 <+76>:  add     a5,a5,a4
     0x8000bdc2 <+78>:  lui     a2,0x40000
     0x8000bdc6 <+82>:  addi    a2,a2,-58 # 0x3fffffc6
     0x8000bdca <+86>:  add     a5,a5,a2
     0x8000bdcc <+88>:  slli    a5,a5,0x2
     0x8000bdce <+90>:  add     a5,a5,a0
     0x8000bdd0 <+92>:  flw     fa5,0(a5)
     0x8000bdd2 <+94>:  j       0x8000bd8e <fused_nn_pad_layout_transform+26>
     0x8000bdd4 <+96>:  fmv.w.x fa5,zero
     0x8000bdd8 <+100>: j       0x8000bd8e <fused_nn_pad_layout_transform+26>
     0x8000bdda <+102>: fmv.w.x fa5,zero
     0x8000bdde <+106>: j       0x8000bd8e <fused_nn_pad_layout_transform+26>
     0x8000bde0 <+108>: li      a0,0
     0x8000bde2 <+110>: ret

  My code breaks on line 0x8000bd8a and then the mcause register is
  loaded with value 0x02 which translates to illegal instruction. Please
  let me know if you need more information about this.

  I also posted this on ZephyrProject in case it is related to the
  Zephyr: https://github.com/zephyrproject-rtos/zephyr/issues/34026

  I have tested on both QEMU 5.1.0 and 5.2.0 versions. I ran the same
  code on qemu riscv64 and didn't have the same problem. Here is the
  assembly code that is generated for the same operation:

  => 0x000000008000b446 <+0>:   ld      a4,0(a0)
     0x000000008000b448 <+2>:   ld      a5,8(a0)
     0x000000008000b44a <+4>:   ld      a0,0(a4)
     0x000000008000b44c <+6>:   ld      a1,0(a5)
     0x000000008000b44e <+8>:   li      a3,0
     0x000000008000b450 <+10>:  j       0x8000b476 
<fused_nn_pad_layout_transform+48>
     0x000000008000b452 <+12>:  addiw   a5,a3,-2
     0x000000008000b456 <+16>:  li      a2,27
     0x000000008000b458 <+18>:  bgeu    a2,a5,0x8000b480 
<fused_nn_pad_layout_transform+58>
     0x000000008000b45c <+22>:  li      a2,0
     0x000000008000b460 <+26>:  slliw   a5,a3,0x5
     0x000000008000b464 <+30>:  addw    a5,a5,a4
     0x000000008000b466 <+32>:  slli    a5,a5,0x2
     0x000000008000b468 <+34>:  add     a5,a5,a1
     0x000000008000b46a <+36>:  sw      a2,0(a5)
     0x000000008000b46c <+38>:  addiw   a4,a4,1
     0x000000008000b46e <+40>:  li      a5,31
     0x000000008000b470 <+42>:  bge     a5,a4,0x8000b452 
<fused_nn_pad_layout_transform+12>
     0x000000008000b474 <+46>:  addiw   a3,a3,1
     0x000000008000b476 <+48>:  li      a5,31
     0x000000008000b478 <+50>:  blt     a5,a3,0x8000b4ac 
<fused_nn_pad_layout_transform+102>
     0x000000008000b47c <+54>:  li      a4,0
     0x000000008000b47e <+56>:  j       0x8000b46e 
<fused_nn_pad_layout_transform+40>
     0x000000008000b480 <+58>:  li      a5,1
     0x000000008000b482 <+60>:  bge     a5,a4,0x8000b4a0 
<fused_nn_pad_layout_transform+90>
     0x000000008000b486 <+64>:  li      a5,29
     0x000000008000b488 <+66>:  blt     a5,a4,0x8000b4a6 
<fused_nn_pad_layout_transform+96>
     0x000000008000b48c <+70>:  li      a5,28
     0x000000008000b48e <+72>:  mulw    a5,a5,a3
     0x000000008000b492 <+76>:  addw    a5,a5,a4
     0x000000008000b494 <+78>:  addiw   a5,a5,-58
     0x000000008000b498 <+82>:  slli    a5,a5,0x2
     0x000000008000b49a <+84>:  add     a5,a5,a0
     0x000000008000b49c <+86>:  lw      a2,0(a5)
     0x000000008000b49e <+88>:  j       0x8000b460 
<fused_nn_pad_layout_transform+26>
     0x000000008000b4a0 <+90>:  li      a2,0
     0x000000008000b4a4 <+94>:  j       0x8000b460 
<fused_nn_pad_layout_transform+26>
     0x000000008000b4a6 <+96>:  li      a2,0
     0x000000008000b4aa <+100>: j       0x8000b460 
<fused_nn_pad_layout_transform+26>
     0x000000008000b4ac <+102>: li      a0,0
     0x000000008000b4ae <+104>: ret

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