[Bug 1923629] Re: RISC-V Vector Instruction vssub.vv not saturating

[Alistair Francis]

This was fixed by commit:

commit 65606f21243a796537bfe4708720a9bf4bb50169
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date:   Fri Feb 12 23:02:21 2021 +0800

    target/riscv: Fixup saturate subtract function
    
    The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
    However, when the predication is ture and a is 0, it should return maximum.
    
    Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


The fix will be in the QEMU 6.1 release.

** Changed in: qemu
       Status: New => Fix Committed

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https://bugs.launchpad.net/bugs/1923629

Title:
  RISC-V Vector Instruction vssub.vv not saturating

Status in QEMU:
  Fix Committed

Bug description:
  I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an
  incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).

  Here is the bit of the code:

                vmv.v.i         v16, 0
                …
  8f040457      vssub.vv        v8,v16,v8

  I believe the instruction encoding is correct (vssub.vv with vd = v8,
  vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.

  I’ve just tested with what I think is the latest branch (
  https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb
  2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still
  exists.

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