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Re: [PULL v3 00/42] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL v3 00/42] riscv-to-apply queue |
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Date: |
Wed, 12 May 2021 19:46:56 +0100 |
On Tue, 11 May 2021 at 11:20, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit e4f3ede95ce813d5705c65e1c0e1c80c70739ebb:
>
> Merge remote-tracking branch
> 'remotes/kraxel/tags/usb-20210505-pull-request' into staging (2021-05-10
> 19:55:06 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210511
>
> for you to fetch changes up to c30a0757f094c107e491820e3d35224eb68859c7:
>
> target/riscv: Fix the RV64H decode comment (2021-05-11 20:02:07 +1000)
>
> ----------------------------------------------------------------
> A large collection of RISC-V fixes, improvements and features
>
> - Clenaup some left over v1.9 code
> - Documentation improvements
> - Support for the shakti_c machine
> - Internal cleanup of the CSR accesses
> - Updates to the OpenTitan platform
> - Support for the virtio-vga
> - Fix for the saturate subtract in vector extensions
> - Experimental support for the ePMP spec
> - A range of other internal code cleanups and bug fixes
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
- [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, (continued)
- [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/11
- [PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/11
- [PULL v3 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/11
- [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/11
- [PULL v3 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/11
- [PULL v3 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/11
- [PULL v3 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/11
- [PULL v3 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/11
- [PULL v3 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/11
- [PULL v3 42/42] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/05/11
- Re: [PULL v3 00/42] riscv-to-apply queue,
Peter Maydell <=