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[PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers
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From: |
Alistair Francis |
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Subject: |
[PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers |
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Date: |
Tue, 11 May 2021 20:19:23 +1000 |
Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.
Also add Bin who has been helping with reviews.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id:
6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
---
MAINTAINERS | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7aaa304b1e..3ace764d29 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -295,9 +295,8 @@ F: tests/acceptance/machine_ppc.py
RISC-V TCG CPUs
M: Palmer Dabbelt <palmer@dabbelt.com>
-M: Alistair Francis <Alistair.Francis@wdc.com>
-M: Sagar Karandikar <sagark@eecs.berkeley.edu>
-M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+M: Alistair Francis <alistair.francis@wdc.com>
+M: Bin Meng <bin.meng@windriver.com>
L: qemu-riscv@nongnu.org
S: Supported
F: target/riscv/
--
2.31.1
- [PULL v3 03/42] target/riscv: Align the data type of reset vector address, (continued)
- [PULL v3 03/42] target/riscv: Align the data type of reset vector address, Alistair Francis, 2021/05/11
- [PULL v3 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/11
- [PULL v3 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/11
- [PULL v3 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/11
- [PULL v3 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/11
- [PULL v3 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/11
- [PULL v3 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/11
- [PULL v3 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/11
- [PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/11
- [PULL v3 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/11
- [PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers,
Alistair Francis <=
- [PULL v3 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/11
- [PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/11
- [PULL v3 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/11
- [PULL v3 19/42] docs: Add documentation for shakti_c machine, Alistair Francis, 2021/05/11
- [PULL v3 18/42] target/riscv: Fixup saturate subtract function, Alistair Francis, 2021/05/11
- [PULL v3 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/11
- [PULL v3 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/11
- [PULL v3 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/11
- [PULL v3 23/42] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/05/11
- [PULL v3 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/11