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[PULL 02/26] linux-user/aarch64: Enable hwcap for RND, BTI, and MTE
From: |
Peter Maydell |
Subject: |
[PULL 02/26] linux-user/aarch64: Enable hwcap for RND, BTI, and MTE |
Date: |
Mon, 10 May 2021 13:25:24 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
These three features are already enabled by TCG, but are missing
their hwcap bits. Update HWCAP2 from linux v5.12.
Cc: qemu-stable@nongnu.org (for 6.0.1)
Buglink: https://bugs.launchpad.net/bugs/1926044
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210427214108.88503-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/elfload.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index c6731013fde..fc9c4f12be9 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -586,6 +586,16 @@ enum {
ARM_HWCAP2_A64_SVESM4 = 1 << 6,
ARM_HWCAP2_A64_FLAGM2 = 1 << 7,
ARM_HWCAP2_A64_FRINT = 1 << 8,
+ ARM_HWCAP2_A64_SVEI8MM = 1 << 9,
+ ARM_HWCAP2_A64_SVEF32MM = 1 << 10,
+ ARM_HWCAP2_A64_SVEF64MM = 1 << 11,
+ ARM_HWCAP2_A64_SVEBF16 = 1 << 12,
+ ARM_HWCAP2_A64_I8MM = 1 << 13,
+ ARM_HWCAP2_A64_BF16 = 1 << 14,
+ ARM_HWCAP2_A64_DGH = 1 << 15,
+ ARM_HWCAP2_A64_RNG = 1 << 16,
+ ARM_HWCAP2_A64_BTI = 1 << 17,
+ ARM_HWCAP2_A64_MTE = 1 << 18,
};
#define ELF_HWCAP get_elf_hwcap()
@@ -640,6 +650,9 @@ static uint32_t get_elf_hwcap2(void)
GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP);
GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2);
GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT);
+ GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
+ GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
+ GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
return hwcaps;
}
--
2.20.1
- [PULL 00/26] target-arm queue, Peter Maydell, 2021/05/10
- [PULL 02/26] linux-user/aarch64: Enable hwcap for RND, BTI, and MTE,
Peter Maydell <=
- [PULL 01/26] docs: fix link in sbsa description, Peter Maydell, 2021/05/10
- [PULL 03/26] target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write(), Peter Maydell, 2021/05/10
- [PULL 04/26] target/arm: Move constant expanders to translate.h, Peter Maydell, 2021/05/10
- [PULL 06/26] target/arm: Make functions used by m-nocp global, Peter Maydell, 2021/05/10
- [PULL 05/26] target/arm: Share unallocated_encoding() and gen_exception_insn(), Peter Maydell, 2021/05/10
- [PULL 07/26] target/arm: Split m-nocp trans functions into their own file, Peter Maydell, 2021/05/10
- [PULL 08/26] target/arm: Move gen_aa32 functions to translate-a32.h, Peter Maydell, 2021/05/10
- [PULL 12/26] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc, Peter Maydell, 2021/05/10
- [PULL 10/26] target/arm: Make functions used by translate-vfp global, Peter Maydell, 2021/05/10
- [PULL 09/26] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc, Peter Maydell, 2021/05/10