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Re: [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() he
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions |
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Date: |
Mon, 10 May 2021 17:23:06 +1000 |
On Thu, May 6, 2021 at 2:26 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
> interfaces for immediate shift instructions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-----------------------
> target/riscv/translate.c | 39 ++++++++++++++++++
> 2 files changed, 43 insertions(+), 50 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index bd93f634cf0..6e736c9d0d1 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -268,54 +268,17 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
> }
> static bool trans_slli(DisasContext *ctx, arg_slli *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_shli_tl(t, t, a->shamt);
> -
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_shl_tl);
> }
>
> static bool trans_srli(DisasContext *ctx, arg_srli *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_shri_tl(t, t, a->shamt);
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_shr_tl);
> }
>
> static bool trans_srai(DisasContext *ctx, arg_srai *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_sari_tl(t, t, a->shamt);
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_sar_tl);
> }
>
> static bool trans_add(DisasContext *ctx, arg_add *a)
> @@ -377,16 +340,7 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
> static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> {
> REQUIRE_64BIT(ctx);
> - TCGv source1;
> - source1 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> -
> - tcg_gen_shli_tl(source1, source1, a->shamt);
> - tcg_gen_ext32s_tl(source1, source1);
> - gen_set_gpr(a->rd, source1);
> -
> - tcg_temp_free(source1);
> - return true;
> + return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
> }
>
> static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5f1a3c694fe..292cf09932d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -652,6 +652,45 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
> target_ulong pc)
> return cpu_ldl_code(env, pc);
> }
>
> +static bool gen_shifti(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> +
> + tcg_gen_movi_tl(source2, a->shamt);
> + (*func)(source1, source1, source2);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +
> +static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + (*func)(source1, source1, source2);
> + tcg_gen_ext32s_tl(source1, source1);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +
> static void gen_ctz(TCGv ret, TCGv arg1)
> {
> tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> --
> 2.17.1
>
>
- [PATCH v6 00/17] support subsets of bitmanip extension, frank . chang, 2021/05/05
- [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2021/05/05
- [PATCH v6 03/17] target/riscv: rvb: count bits set, frank . chang, 2021/05/05
- [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2021/05/05
- [PATCH v6 05/17] target/riscv: rvb: pack two words into one register, frank . chang, 2021/05/05
- [PATCH v6 04/17] target/riscv: rvb: logic-with-negate, frank . chang, 2021/05/05
- [PATCH v6 06/17] target/riscv: rvb: min/max instructions, frank . chang, 2021/05/05
- [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions, frank . chang, 2021/05/05
- [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, frank . chang, 2021/05/05
- Re: [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions,
Alistair Francis <=
- [PATCH v6 09/17] target/riscv: rvb: single-bit instructions, frank . chang, 2021/05/05
- [PATCH v6 10/17] target/riscv: rvb: shift ones, frank . chang, 2021/05/05
- [PATCH v6 11/17] target/riscv: rvb: rotate (left/right), frank . chang, 2021/05/05
- [PATCH v6 12/17] target/riscv: rvb: generalized reverse, frank . chang, 2021/05/05
- [PATCH v6 13/17] target/riscv: rvb: generalized or-combine, frank . chang, 2021/05/05
- [PATCH v6 14/17] target/riscv: rvb: address calculation, frank . chang, 2021/05/05
- [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend, frank . chang, 2021/05/05