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[PULL v2 29/42] target/riscv: fix exception index on instruction access
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From: |
Alistair Francis |
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Subject: |
[PULL v2 29/42] target/riscv: fix exception index on instruction access fault |
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Date: |
Thu, 6 May 2021 09:22:59 +1000 |
From: Emmanuel Blot <emmanuel.blot@sifive.com>
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 659ca8a173..1018c0036d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -694,8 +694,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
if (access_type == MMU_DATA_STORE) {
cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
- } else {
+ } else if (access_type == MMU_DATA_LOAD) {
cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+ } else {
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
}
env->badaddr = addr;
--
2.31.1
- [PULL v2 19/42] docs: Add documentation for shakti_c machine, (continued)
- [PULL v2 19/42] docs: Add documentation for shakti_c machine, Alistair Francis, 2021/05/05
- [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/05
- [PULL v2 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/05
- [PULL v2 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/05
- [PULL v2 23/42] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/05/05
- [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/05
- [PULL v2 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/05
- [PULL v2 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/05
- [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/05
- [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/05
- [PULL v2 29/42] target/riscv: fix exception index on instruction access fault,
Alistair Francis <=
- [PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector, Alistair Francis, 2021/05/05
- [PULL v2 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/05
- [PULL v2 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions, Alistair Francis, 2021/05/05
- [PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/05
- [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/05
- [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/05
- [PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/05
- [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/05
- [PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/05
- [PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/05