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[PULL 02/42] docs/system/generic-loader.rst: Fix style
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From: |
Alistair Francis |
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Subject: |
[PULL 02/42] docs/system/generic-loader.rst: Fix style |
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Date: |
Tue, 4 May 2021 08:12:47 +1000 |
From: Axel Heider <axelheider@gmx.de>
Fix style to have a proper description of the parameter 'force-raw'.
Signed-off-by: Axel Heider <axelheider@gmx.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/generic-loader.rst | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst
index 6bf8a4eb48..531ddbc8e3 100644
--- a/docs/system/generic-loader.rst
+++ b/docs/system/generic-loader.rst
@@ -92,9 +92,12 @@ shown below:
specified in the executable format header. This option should only
be used for the boot image. This will also cause the image to be
written to the specified CPU's address space. If not specified, the
- default is CPU 0. <force-raw> - Setting force-raw=on forces the file
- to be treated as a raw image. This can be used to load supported
- executable formats as if they were raw.
+ default is CPU 0.
+
+``<force-raw>``
+ Setting 'force-raw=on' forces the file to be treated as a raw image.
+ This can be used to load supported executable formats as if they
+ were raw.
All values are parsed using the standard QemuOpts parsing. This allows the user
to specify any values in any format supported. By default the values
--
2.31.1
- [PULL 00/42] riscv-to-apply queue, Alistair Francis, 2021/05/03
- [PULL 02/42] docs/system/generic-loader.rst: Fix style,
Alistair Francis <=
- [PULL 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/03
- [PULL 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/03
- [PULL 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/03
- [PULL 01/42] target/riscv: Remove privilege v1.9 specific CSR related code, Alistair Francis, 2021/05/03
- [PULL 03/42] target/riscv: Align the data type of reset vector address, Alistair Francis, 2021/05/03
- [PULL 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[], Alistair Francis, 2021/05/03
- [PULL 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/03
- [PULL 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/03
- [PULL 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/03
- [PULL 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/03