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[PULL 05/31] target/hexagon: remove unnecessary semicolons
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From: |
Richard Henderson |
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Subject: |
[PULL 05/31] target/hexagon: remove unnecessary semicolons |
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Date: |
Sat, 1 May 2021 11:42:58 -0700 |
From: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reported-by: Richard Henderson <<richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1615784100-26459-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/gen_tcg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index e044deaff2..a30048ee57 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -83,9 +83,9 @@
#define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE
#define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE
#define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE
-#define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE;
+#define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE
#define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE
-#define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE;
+#define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE
#define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE
#define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE
#define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE
--
2.25.1
- [PULL 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM, (continued)
- [PULL 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM, Richard Henderson, 2021/05/01
- [PULL 06/31] Hexagon (target/hexagon) TCG generation cleanup, Richard Henderson, 2021/05/01
- [PULL 08/31] Hexagon (target/hexagon) remove unnecessary inline directives, Richard Henderson, 2021/05/01
- [PULL 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu, Richard Henderson, 2021/05/01
- [PULL 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time, Richard Henderson, 2021/05/01
- [PULL 12/31] Hexagon (target/hexagon) change variables from int to bool when appropriate, Richard Henderson, 2021/05/01
- [PULL 16/31] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn, Richard Henderson, 2021/05/01
- [PULL 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair, Richard Henderson, 2021/05/01
- [PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN, Richard Henderson, 2021/05/01
- [PULL 13/31] Hexagon (target/hexagon) remove unused carry_from_add64 function, Richard Henderson, 2021/05/01
- [PULL 05/31] target/hexagon: remove unnecessary semicolons,
Richard Henderson <=
- [PULL 14/31] Hexagon (target/hexagon) change type of softfloat_roundingmodes, Richard Henderson, 2021/05/01
- [PULL 17/31] Hexagon (target/hexagon) use softfloat for float-to-int conversions, Richard Henderson, 2021/05/01
- [PULL 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess, Richard Henderson, 2021/05/01
- [PULL 18/31] Hexagon (target/hexagon) cleanup ternary operators in semantics, Richard Henderson, 2021/05/01
- [PULL 20/31] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h, Richard Henderson, 2021/05/01
- [PULL 26/31] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c, Richard Henderson, 2021/05/01
- [PULL 19/31] Hexagon (target/hexagon) cleanup reg_field_info definition, Richard Henderson, 2021/05/01
- [PULL 24/31] Hexagon (target/hexagon) add A5_ACS (vacsh), Richard Henderson, 2021/05/01
- [PULL 23/31] Hexagon (target/hexagon) add F2_sfinvsqrta, Richard Henderson, 2021/05/01
- [PULL 22/31] Hexagon (target/hexagon) add F2_sfrecipa instruction, Richard Henderson, 2021/05/01