Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification

[LIU Zhiwei]

On 2021/4/20 下午2:26, Alistair Francis wrote:
> On Tue, Apr 20, 2021 at 11:45 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> > On 2021/4/20 上午7:30, Alistair Francis wrote:
> > > On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> > > > This patch set gives an implementation of "RISC-V Core-Local Interrupt
> > > > Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where
> > > > you can find the pdf format or the source code.
> > > >
> > > > I take over the job from Michael Clark, who gave the first implementation
> > > > of clic-v0.7 specification. If there is any copyright question, please
> > > > let me know.
> > > You need to make sure you leave all original copyright notices and SoB in place.
> > OK.
> >
> > Is it OK that keep the original copyright notices for new files and
> > your SoB in every patch,  Michael?
> >
> > > > Features:
> > > > 1. support four kinds of trigger types.
> > > > 2. Preserve the CSR WARL/WPRI semantics.
> > > > 3. Option to select different modes, such as M/S/U or M/U.
> > > > 4. At most 4096 interrupts.
> > > > 5. At most 1024 apertures.
> > > >
> > > > Todo:
> > > > 1. Encode the interrupt trigger information to exccode.
> > > > 2. Support complete CSR mclicbase when its number is fixed.
> > > > 3. Gave each aperture an independend address.
> > > >
> > > > It have passed my qtest case and freertos test. Welcome to have a try
> > > > for your hardware.
> > > It doesn't seem to be connected to any machine. How are you testing this?
> > There is a machine called SMARTL in my repository[1].  The qtest case
> > is  tests/qtest/test-riscv32-clic.c. If it's better, I can upstream the
> > machine together next version.
> I don't really want to add a new hardware device when it isn't
> connected to a machine. It would be great if we could connect it to a
> machine. If not SMARTL maybe we could add it as an option to the virt
> machine?
Currently it is good to  connect CLIC to virt machine.  I can fix it in 
the next version if it is OK for you.
> What is SMARTL? Is that a publically available board?

SMARTL is a fpga evaluation board.  We usually use it  to debug programs 
for XuanTie CPU serials.
It has a 32bit CPU, 1 UART,  4 timers, and the CLIC interrupt 
controller. I will give  a detailed documentation
when I upstream it.

There are still many other  RISC-V boards, but more complex. I plan to 
upstream the XuanTie CPU
and  some widely used boards after the P extension and CLIC.

Zhiwei

> Alistair
>
> > Zhiwei
> >
> > [1]https://github.com/romanheros/qemu, branch: riscv-clic-upstream-rfc
> >
> >
> > > Alistair
> > >
> > > > Any advice is welcomed. Thanks very much.
> > > >
> > > > Zhiwei
> > > >
> > > > [1] specification website: https://github.com/riscv/riscv-fast-interrupt.
> > > > [2] Michael Clark origin work: 
> > > > https://github.com/sifive/riscv-qemu/tree/sifive-clic.
> > > >
> > > >
> > > > LIU Zhiwei (11):
> > > >     target/riscv: Add CLIC CSR mintstatus
> > > >     target/riscv: Update CSR xintthresh in CLIC mode
> > > >     hw/intc: Add CLIC device
> > > >     target/riscv: Update CSR xie in CLIC mode
> > > >     target/riscv: Update CSR xip in CLIC mode
> > > >     target/riscv: Update CSR xtvec in CLIC mode
> > > >     target/riscv: Update CSR xtvt in CLIC mode
> > > >     target/riscv: Update CSR xnxti in CLIC mode
> > > >     target/riscv: Update CSR mclicbase in CLIC mode
> > > >     target/riscv: Update interrupt handling in CLIC mode
> > > >     target/riscv: Update interrupt return in CLIC mode
> > > >
> > > >    default-configs/devices/riscv32-softmmu.mak |   1 +
> > > >    default-configs/devices/riscv64-softmmu.mak |   1 +
> > > >    hw/intc/Kconfig                             |   3 +
> > > >    hw/intc/meson.build                         |   1 +
> > > >    hw/intc/riscv_clic.c                        | 836 ++++++++++++++++++++
> > > >    include/hw/intc/riscv_clic.h                | 103 +++
> > > >    target/riscv/cpu.h                          |   9 +
> > > >    target/riscv/cpu_bits.h                     |  32 +
> > > >    target/riscv/cpu_helper.c                   | 117 ++-
> > > >    target/riscv/csr.c                          | 247 +++++-
> > > >    target/riscv/op_helper.c                    |  25 +
> > > >    11 files changed, 1363 insertions(+), 12 deletions(-)
> > > >    create mode 100644 hw/intc/riscv_clic.c
> > > >    create mode 100644 include/hw/intc/riscv_clic.h
> > > >
> > > > --
> > > > 2.25.1