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RE: [PATCH 10/15] Hexagon (target/hexagon) instructions with multiple de


From: Taylor Simpson
Subject: RE: [PATCH 10/15] Hexagon (target/hexagon) instructions with multiple definitions
Date: Mon, 29 Mar 2021 21:55:47 +0000


> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Thursday, March 25, 2021 11:25 AM
> To: Taylor Simpson <tsimpson@quicinc.com>; qemu-devel@nongnu.org
> Cc: philmd@redhat.com; ale@rev.ng; Brian Cain <bcain@quicinc.com>
> Subject: Re: [PATCH 10/15] Hexagon (target/hexagon) instructions with
> multiple definitions
>
> On 3/24/21 8:50 PM, Taylor Simpson wrote:
> > Instructions with multiple definitions require special handling
> > because the generator wants to create a helper, but helpers can
> > only return a single result.  Therefore, we must override the
> > generated code.
> >
> > The following instructions are added
> >      A4_addp_c        Rdd32 = add(Rss32, Rtt32, Px4):carry
> >                           Add with carry
> >      A4_subp_c        Rdd32 = sub(Rss32, Rtt32, Px4):carry
> >                           Sub with carry
> >      A5_ACS           Rxx32,Pe4 = vacsh(Rss32, Rtt32)
> >                           Add compare and select elements of two vectors
> >      A6_vminub_RdP    Rdd32,Pe4 = vminub(Rtt32, Rss32)
> >                           Vector min of bytes
> >      F2_invsqrta      Rd32,Pe4 = sfinvsqrta(Rs32)
> >                           Square root approx
> >      F2_sfrecipa      Rd32,Pe4 = sfrecipa(Rs32, Rt32)
> >                           Recripocal approx
>
> One thing at a time.  This is no longer port bring-up where large patches are
> unavoidable.

I can divide this one up into smaller pieces.  However, I'll ask for general 
leniency since I'm still adding scalar core instructions that were withheld 
from the original series in order to reduce the initial review burden.

Thanks,
Taylor



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