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[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
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From: |
Alistair Francis |
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Subject: |
[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV |
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Date: |
Mon, 22 Mar 2021 21:57:48 -0400 |
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b15a60d8a2..8d4a62988d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -364,7 +364,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
use_background = true;
}
--
2.30.1
- [PULL 00/16] riscv-to-apply queue, Alistair Francis, 2021/03/22
- [PULL 01/16] target/riscv: fix vs() to return proper error code, Alistair Francis, 2021/03/22
- [PULL 02/16] hw/char: disable ibex uart receive if the buffer is full, Alistair Francis, 2021/03/22
- [PULL 03/16] target/riscv: propagate PMP permission to TLB page, Alistair Francis, 2021/03/22
- [PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed, Alistair Francis, 2021/03/22
- [PULL 04/16] target/riscv: add log of PMP permission checking, Alistair Francis, 2021/03/22
- [PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions, Alistair Francis, 2021/03/22
- [PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV,
Alistair Francis <=
- [PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip, Alistair Francis, 2021/03/22
- [PULL 09/16] hw/riscv: Add fw_cfg support to virt, Alistair Francis, 2021/03/22
- [PULL 10/16] hw/riscv: allow ramfb on virt, Alistair Francis, 2021/03/22
- [PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie, Alistair Francis, 2021/03/22
- [PULL 12/16] target/riscv: Add proper two-stage lookup exception detection, Alistair Francis, 2021/03/22
- [PULL 13/16] hw/block: m25p80: Support fast read for SST flashes, Alistair Francis, 2021/03/22
- [PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register, Alistair Francis, 2021/03/22
- [PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine, Alistair Francis, 2021/03/22
- [PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions, Alistair Francis, 2021/03/22
- Re: [PULL 00/16] riscv-to-apply queue, Peter Maydell, 2021/03/23