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[PULL 3/7] target/tricore: Pass MMUAccessType to get_physical_address()
From: |
Bastian Koppelmann |
Subject: |
[PULL 3/7] target/tricore: Pass MMUAccessType to get_physical_address() |
Date: |
Sun, 14 Mar 2021 14:55:09 +0100 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
'int access_type' and ACCESS_INT are unused, drop them.
Provide the mmu_idx argument to match other targets.
'int rw' is actually the MMUAccessType, rename it.
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210127224255.3505711-3-f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 81171db833..c5e997f321 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -33,7 +33,7 @@ enum {
#if defined(CONFIG_SOFTMMU)
static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
int *prot, target_ulong address,
- int rw, int access_type)
+ MMUAccessType access_type, int mmu_idx)
{
int ret = TLBRET_MATCH;
@@ -72,13 +72,11 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
CPUTriCoreState *env = &cpu->env;
hwaddr physical;
int prot;
- int access_type;
int ret = 0;
rw &= 1;
- access_type = ACCESS_INT;
ret = get_physical_address(env, &physical, &prot,
- address, rw, access_type);
+ address, rw, mmu_idx);
qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical "
TARGET_FMT_plx " prot %d\n",
--
2.30.1
- [PULL 0/7] tricore queue, Bastian Koppelmann, 2021/03/14
- [PULL 2/7] target/tricore: Replace magic value by MMU_DATA_LOAD definition, Bastian Koppelmann, 2021/03/14
- [PULL 1/7] tricore: added triboard with tc27x_soc, Bastian Koppelmann, 2021/03/14
- [PULL 3/7] target/tricore: Pass MMUAccessType to get_physical_address(),
Bastian Koppelmann <=
- [PULL 4/7] target/tricore: Remove unused definitions, Bastian Koppelmann, 2021/03/14
- [PULL 5/7] tricore: fixed faulty conditions for extr and imask, Bastian Koppelmann, 2021/03/14
- [PULL 6/7] target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2, Bastian Koppelmann, 2021/03/14
- [PULL 7/7] target/tricore: Fix OPC2_32_RRPW_EXTR for width=0, Bastian Koppelmann, 2021/03/14
- Re: [PULL 0/7] tricore queue, Peter Maydell, 2021/03/15