On Thu, 11 Mar 2021 at 02:59, LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
Currently, I am writing an interrupt controller (CLIC) for RISC-V. I can't find a good way to process edge-triggered interrupt.
According to edge-triggered definition, if I select an edge-triggered interrupt to serve , it will clean its pending status. However after serving the interrupt, there is no chance to select other pending interrupts.
I have two methods.
One is to add a timer for interrupt controller, so that every pending interrupt can be served at some point.
The other is that always pull a pending interrupt to serve at the interrupt return instruction.
You should do what the hardware you're modelling does. I'm
pretty sure it won't be using a timer, at any rate. Whether
it does something on interrupt-return insns will depend on
the architecture and how tightly the interrupt controller
is integrated with the CPU.
In general edge-triggered interrupts for an interrupt
controller just mean "when it sees a 0->1 transition
on its input line it does something, eg mark the interrupt
pending", and also usually "when the guest OS acknowledges
the interrupt (eg via a register write to the interrupt
controller), mark the interrupt as no longer pending", and
a "keep telling the OS that there is an available interrupt
of some kind until all the interrupts are no longer pending".
Thanks very much. It solves the most problem. However, I still have
a little one.