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Re: [PATCH RESEND 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [PATCH RESEND 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole |
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Date: |
Tue, 9 Mar 2021 18:14:59 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 |
On 3/9/21 4:52 PM, BALATON Zoltan wrote:
> On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:
>> Per the comment in the Malta board, the [0x0000.0000-0x2000.0000]
>> range is decoded by the GT64120, so move the "empty_slot" there.
>
> I don't know anything about it to be able to review but is this a
> feature of the GT64120 chip (in which case the change is correct) or the
> Malta board (in which case this might make the GT64120 model board
> specific that may not matter much as there's nothing else using it now).
As this is board-specific, I'll improve the description. Let's ignore
this patch for now.
Thank you for the previous reviews :)
Phil.
- Re: [PATCH RESEND 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers, (continued)
- [PATCH RESEND 3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats, Philippe Mathieu-Daudé, 2021/03/09
- [PATCH RESEND 4/6] hw/mips/gt64xxx: Rename trace events related to interrupt registers, Philippe Mathieu-Daudé, 2021/03/09
- [PATCH RESEND 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers, Philippe Mathieu-Daudé, 2021/03/09
- [PATCH RESEND 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole, Philippe Mathieu-Daudé, 2021/03/09
- Re: [PATCH RESEND 0/6] hw/mips/gt64120: Minor fixes, Philippe Mathieu-Daudé, 2021/03/11