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[RFC PATCH v2 03/22] target/mips/translate: Make gen_rdhwr() public
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH v2 03/22] target/mips/translate: Make gen_rdhwr() public |
Date: |
Tue, 9 Mar 2021 15:56:34 +0100 |
We will use gen_rdhwr() outside of translate.c, make it public.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-28-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 2 ++
target/mips/translate.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index e4f2f26de89..2b3c7a69ec6 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -148,6 +148,8 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv
arg0, TCGv arg1);
bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
+void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
+
extern TCGv cpu_gpr[32], cpu_PC;
#if defined(TARGET_MIPS64)
extern TCGv_i64 cpu_gpr_hi[32];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0131affce70..0f77c0ebc57 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12349,7 +12349,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t
opc,
}
}
-static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
+void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
{
TCGv t0;
--
2.26.2
- [RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 01/22] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 02/22] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 03/22] target/mips/translate: Make gen_rdhwr() public,
Philippe Mathieu-Daudé <=
- [RFC PATCH v2 04/22] target/mips/translate: Simplify PCPYH using deposit_i64(), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 05/22] target/mips/tx79: Move PCPYH opcode to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 06/22] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 07/22] target/mips: Remove 'C790 Multimedia Instructions' dead code, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 08/22] target/mips/tx79: Salvage instructions description comment, Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 09/22] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 10/22] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), Philippe Mathieu-Daudé, 2021/03/09
- [RFC PATCH v2 11/22] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/03/09