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[RFC v5 12/36] target/arm: only perform TCG cpu and machine inits if TCG
From: |
Claudio Fontana |
Subject: |
[RFC v5 12/36] target/arm: only perform TCG cpu and machine inits if TCG enabled |
Date: |
Tue, 9 Mar 2021 15:25:20 +0100 |
of note, cpreg lists were previously initialized by TCG first,
and then thrown away and replaced with the data coming from KVM.
Now we just initialize once, either for TCG or for KVM.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu.c | 32 ++++++++++++++++++--------------
target/arm/kvm.c | 18 +++++++++---------
target/arm/machine.c | 20 +++++++++++++-------
3 files changed, 40 insertions(+), 30 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7a21944d43..88e866cc8f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -436,9 +436,11 @@ static void arm_cpu_reset(DeviceState *dev)
}
#endif
- hw_breakpoint_update_all(cpu);
- hw_watchpoint_update_all(cpu);
- arm_rebuild_hflags(env);
+ if (tcg_enabled()) {
+ hw_breakpoint_update_all(cpu);
+ hw_watchpoint_update_all(cpu);
+ arm_rebuild_hflags(env);
+ }
}
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
@@ -1319,6 +1321,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
}
+#ifdef CONFIG_TCG
{
uint64_t scale;
@@ -1344,7 +1347,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
arm_gt_hvtimer_cb, cpu);
}
-#endif
+#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
@@ -1645,17 +1649,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
unset_feature(env, ARM_FEATURE_PMU);
}
if (arm_feature(env, ARM_FEATURE_PMU)) {
- pmu_init(cpu);
-
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
+ pmu_init(cpu);
arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
- }
#ifndef CONFIG_USER_ONLY
- cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
- cpu);
+ cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
+ cpu);
#endif
+ }
} else {
cpu->isar.id_aa64dfr0 =
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
@@ -1738,10 +1741,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
set_feature(env, ARM_FEATURE_VBAR);
}
- register_cp_regs_for_features(cpu);
- arm_cpu_register_gdb_regs_for_features(cpu);
-
- init_cpreg_list(cpu);
+ if (tcg_enabled()) {
+ register_cp_regs_for_features(cpu);
+ arm_cpu_register_gdb_regs_for_features(cpu);
+ init_cpreg_list(cpu);
+ }
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 00e124c812..e04aa7281a 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -429,9 +429,11 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu,
uint64_t regidx)
return &cpu->cpreg_values[res - cpu->cpreg_indexes];
}
-/* Initialize the ARMCPU cpreg list according to the kernel's
- * definition of what CPU registers it knows about (and throw away
- * the previous TCG-created cpreg list).
+/*
+ * Initialize the ARMCPU cpreg list according to the kernel's
+ * definition of what CPU registers it knows about.
+ *
+ * The parallel for TCG is init_cpreg_list() in tcg/
*/
int kvm_arm_init_cpreg_list(ARMCPU *cpu)
{
@@ -473,12 +475,10 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu)
arraylen++;
}
- cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
- cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
- cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
- arraylen);
- cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
- arraylen);
+ cpu->cpreg_indexes = g_new(uint64_t, arraylen);
+ cpu->cpreg_values = g_new(uint64_t, arraylen);
+ cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
+ cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
cpu->cpreg_array_len = arraylen;
cpu->cpreg_vmstate_array_len = arraylen;
diff --git a/target/arm/machine.c b/target/arm/machine.c
index e568662cca..2982e8d7f4 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -2,6 +2,7 @@
#include "cpu.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "kvm_arm.h"
#include "internals.h"
#include "migration/cpu.h"
@@ -635,7 +636,7 @@ static int cpu_pre_save(void *opaque)
{
ARMCPU *cpu = opaque;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_start(&cpu->env);
}
@@ -670,7 +671,7 @@ static int cpu_post_save(void *opaque)
{
ARMCPU *cpu = opaque;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_finish(&cpu->env);
}
@@ -689,7 +690,7 @@ static int cpu_pre_load(void *opaque)
*/
env->irq_line_state = UINT32_MAX;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_start(&cpu->env);
}
@@ -759,13 +760,13 @@ static int cpu_post_load(void *opaque, int version_id)
}
}
- hw_breakpoint_update_all(cpu);
- hw_watchpoint_update_all(cpu);
+ if (tcg_enabled()) {
+ hw_breakpoint_update_all(cpu);
+ hw_watchpoint_update_all(cpu);
- if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
+ arm_rebuild_hflags(&cpu->env);
}
- arm_rebuild_hflags(&cpu->env);
return 0;
}
@@ -815,8 +816,13 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
VMSTATE_UINT32(env.exception.fsr, ARMCPU),
VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
+#ifdef CONFIG_TCG
VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
+#else
+ VMSTATE_UNUSED(sizeof(QEMUTimer *)),
+ VMSTATE_UNUSED(sizeof(QEMUTimer *)),
+#endif /* CONFIG_TCG */
{
.name = "power_state",
.version_id = 0,
--
2.26.2
- [RFC v5 04/36] target/arm: tcg: add sysemu and user subsirs, (continued)
- [RFC v5 04/36] target/arm: tcg: add sysemu and user subsirs, Claudio Fontana, 2021/03/09
- [RFC v5 02/36] target/arm: move helpers to tcg/, Claudio Fontana, 2021/03/09
- [RFC v5 01/36] target/arm: move translate modules to tcg/, Claudio Fontana, 2021/03/09
- [RFC v5 03/36] arm: tcg: only build under CONFIG_TCG, Claudio Fontana, 2021/03/09
- [RFC v5 05/36] target/arm: only build psci for TCG, Claudio Fontana, 2021/03/09
- [RFC v5 06/36] target/arm: split off cpu-sysemu.c, Claudio Fontana, 2021/03/09
- [RFC v5 07/36] target/arm: move physical address translation to cpu-mmu, Claudio Fontana, 2021/03/09
- [RFC v5 08/36] target/arm: cpu-mmu: fix comment style, Claudio Fontana, 2021/03/09
- [RFC v5 10/36] target/arm: cpregs: fix style (mostly just comments), Claudio Fontana, 2021/03/09
- [RFC v5 11/36] target/arm: move cpu definitions to common cpu module, Claudio Fontana, 2021/03/09
- [RFC v5 12/36] target/arm: only perform TCG cpu and machine inits if TCG enabled,
Claudio Fontana <=
- [RFC v5 13/36] target/arm: kvm: add stubs for some helpers, Claudio Fontana, 2021/03/09
- [RFC v5 15/36] target/arm: add temporary stub for arm_rebuild_hflags, Claudio Fontana, 2021/03/09
- [RFC v5 14/36] target/arm: move cpsr_read, cpsr_write to cpu_common, Claudio Fontana, 2021/03/09
- [RFC v5 19/36] target/arm: move arm_sctlr away from tcg helpers, Claudio Fontana, 2021/03/09
- [RFC v5 09/36] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/03/09
- [RFC v5 23/36] target/arm: move sve_exception_el out of TCG helpers, Claudio Fontana, 2021/03/09
- [RFC v5 16/36] target/arm: split vfp state setting from tcg helpers, Claudio Fontana, 2021/03/09
- [RFC v5 20/36] target/arm: move arm_cpu_list to common_cpu, Claudio Fontana, 2021/03/09
- [RFC v5 17/36] target/arm: move arm_mmu_idx* to cpu-mmu, Claudio Fontana, 2021/03/09
- [RFC v5 26/36] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/03/09