Re: [PULL 00/54] target-arm queue

[no-reply]

Patchew URL: 
20210308173244.20710-1-peter.maydell@linaro.org/">https://patchew.org/QEMU/20210308173244.20710-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210308173244.20710-1-peter.maydell@linaro.org
Subject: [PULL 00/54] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20210225091435.644762-1-eric.auger@redhat.com -> 
patchew/20210225091435.644762-1-eric.auger@redhat.com
 - [tag update]      patchew/20210303195339.GB3793@redhat.com -> 
patchew/20210303195339.GB3793@redhat.com
 - [tag update]      patchew/20210308154633.158915-1-thuth@redhat.com -> 
patchew/20210308154633.158915-1-thuth@redhat.com
 * [new tag]         patchew/20210308173244.20710-1-peter.maydell@linaro.org -> 
patchew/20210308173244.20710-1-peter.maydell@linaro.org
Switched to a new branch 'test'
07374e1 hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
fea8e80 hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
b9f3dfd hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
9e3a610 hw/ssi: xilinx_spips: Clean up coding convention issues
bfdae5f hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
d95d2c2 hw/arm: xlnx-zynqmp: Clean up coding convention issues
b52474c hw/dma: Implement a Xilinx CSU DMA model
f8734d1 target/arm: Restrict v7A TCG cpus to TCG accel
97246f4 tests/qtest/sse-timer-test: Test counter scaling changes
bc7ce41 tests/qtest/sse-timer-test: Test the system timer
1ae3cd2 tests/qtest/sse-timer-test: Add simple test of the SSE counter
3c89ac9 docs/system/arm/mps2.rst: Document the new mps3-an547 board
b2cb63d hw/arm/mps2-tz: Add new mps3-an547 board
feee059 hw/arm/mps2-tz: Make initsvtor0 setting board-specific
654d5b5 hw/arm/mps2-tz: Support running APB peripherals on different clock
84a76c5 hw/misc/mps2-scc: Implement changes for AN547
8225557 hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
16fac9b hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
34606d7 hw/arm/mps2-tz: Make UART overflow IRQ board-specific
19c7e52 hw/arm/armsse: Add SSE-300 support
f6003ee hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
c6f883c hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo
73393b5 hw/arm/armsse: Add support for SSE variants with a system counter
45df240 hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo
9fff473 hw/arm/armsse: Add missing SSE-200 SYS_PPU
7222997 hw/arm/armsse: Move PPUs into data-driven framework
2ef7ec8 hw/arm/armsse: Move sysctl register block into data-driven framework
18a85f7 hw/arm/armsse: Move sysinfo register block into data-driven framework
e4ee1e7 hw/arm/armsse: Move s32ktimer into data-driven framework
8655f07 hw/arm/armsse: Move watchdogs into data-driven framework
f827989 hw/arm/armsse: Move dual-timer device into data-driven framework
79b53b8 hw/arm/armsse: Add framework for data-driven device placement
516eaef hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
517dfb6 hw/arm/armsse: Use an array for apb_ppc fields in the state structure
3d20d2e hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
e6df0f6 hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc
9049fd0 hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values
2908277 hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE 
registers
2c929f1 hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL 
register
5132688 hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
8055482 hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300
4d1f059 hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour
3e2ac76 hw/timer/sse-timer: Model the SSE Subsystem System Timer
907d495 hw/timer/sse-counter: Model the SSE Subsystem System Counter
a496eee hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
093c68d hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300
d75dd6e hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values
122ac7a hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values
44fafc0 hw/misc/iotkit-sysctl: Remove is_sse200 flag
a7dd089 hw/arm/armsse: Introduce SSE subsystem version property
9b76681 hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks()
7d51138 clock: Add clock_ns_to_ticks() function
cc6d5be clock: Add ClockPreUpdate callback event type
8a5be7d clock: Add ClockEvent parameter to callbacks

=== OUTPUT BEGIN ===
1/54 Checking commit 8a5be7df4d6d (clock: Add ClockEvent parameter to callbacks)
WARNING: line over 80 characters
#554: FILE: hw/misc/zynq_slcr.c:580:
+    QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback, 
ClockUpdate),

total: 0 errors, 1 warnings, 592 lines checked

Patch 1/54 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/54 Checking commit cc6d5beb5b61 (clock: Add ClockPreUpdate callback event 
type)
3/54 Checking commit 7d5113835fc0 (clock: Add clock_ns_to_ticks() function)
4/54 Checking commit 9b76681ce61a (hw/timer/npcm7xx_timer: Use new 
clock_ns_to_ticks())
5/54 Checking commit a7dd089a76a1 (hw/arm/armsse: Introduce SSE subsystem 
version property)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#132: 
new file mode 100644

total: 0 errors, 1 warnings, 129 lines checked

Patch 5/54 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/54 Checking commit 44fafc03d01f (hw/misc/iotkit-sysctl: Remove is_sse200 flag)
WARNING: line over 80 characters
#247: FILE: hw/misc/iotkit-sysctl.c:375:
+            qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV 
unimplemented\n");

WARNING: line over 80 characters
#262: FILE: hw/misc/iotkit-sysctl.c:387:
+            qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE 
unimplemented\n");

WARNING: line over 80 characters
#393: FILE: hw/misc/iotkit-sysctl.c:489:
+            qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE 
unimplemented\n");

total: 0 errors, 3 warnings, 392 lines checked

Patch 6/54 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/54 Checking commit 122ac7a4273b (hw/misc/iotkit-secctl.c: Implement SSE-300 
PID register values)
8/54 Checking commit d75dd6eea605 (hw/misc/iotkit-sysinfo.c: Implement SSE-300 
PID register values)
9/54 Checking commit 093c68d7ae3d (hw/arm/armsse.c: Use correct SYS_CONFIG0 
register value for SSE-300)
10/54 Checking commit a496eeea5dfd (hw/misc/iotkit-sysinfo.c: Implement 
SYS_CONFIG1 and IIDR)
11/54 Checking commit 907d4959db36 (hw/timer/sse-counter: Model the SSE 
Subsystem System Counter)
12/54 Checking commit 3e2ac7637549 (hw/timer/sse-timer: Model the SSE Subsystem 
System Timer)
WARNING: line over 80 characters
#527: FILE: hw/timer/sse-timer.c:443:
+    DEFINE_PROP_LINK("counter", SSETimer, counter, TYPE_SSE_COUNTER, 
SSECounter *),

total: 0 errors, 1 warnings, 561 lines checked

Patch 12/54 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/54 Checking commit 4d1f059cd9e6 (hw/misc/iotkit-sysctl: Add SSE-300 cases 
which match SSE-200 behaviour)
14/54 Checking commit 8055482d8e88 (hw/misc/iotkit-sysctl: Handle CPU_WAIT, 
NMI_ENABLE for SSE-300)
WARNING: line over 80 characters
#164: FILE: hw/misc/iotkit-sysctl.c:481:
+            qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE 
unimplemented\n");

total: 0 errors, 1 warnings, 138 lines checked

Patch 14/54 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/54 Checking commit 513268884e16 (hw/misc/iotkit-sysctl: Handle INITSVTOR* 
for SSE-300)
16/54 Checking commit 2c929f1573cd (hw/misc/iotkit-sysctl: Implement dummy 
version of SSE-300 PWRCTRL register)
17/54 Checking commit 2908277c9728 (hw/misc/iotkit-sysctl: Handle SSE-300 
changes to PDCM_PD_*_SENSE registers)
18/54 Checking commit 9049fd01810a (hw/misc/iotkit-sysctl: Implement SSE-200 
and SSE-300 PID register values)
19/54 Checking commit e6df0f693f79 (hw/arm/Kconfig: Move ARMSSE_CPUID and 
ARMSSE_MHU stanzas to hw/misc)
20/54 Checking commit 3d20d2ef460e (hw/misc/sse-cpu-pwrctrl: Implement SSE-300 
CPU<N>_PWRCTRL register block)
21/54 Checking commit 517dfb60ff4f (hw/arm/armsse: Use an array for apb_ppc 
fields in the state structure)
22/54 Checking commit 516eaef11830 (hw/arm/armsse: Add a define for number of 
IRQs used by the SSE itself)
23/54 Checking commit 79b53b897cc5 (hw/arm/armsse: Add framework for 
data-driven device placement)
24/54 Checking commit f82798971026 (hw/arm/armsse: Move dual-timer device into 
data-driven framework)
25/54 Checking commit 8655f0723679 (hw/arm/armsse: Move watchdogs into 
data-driven framework)
26/54 Checking commit e4ee1e70d8e7 (hw/arm/armsse: Move s32ktimer into 
data-driven framework)
27/54 Checking commit 18a85f7322cf (hw/arm/armsse: Move sysinfo register block 
into data-driven framework)
28/54 Checking commit 2ef7ec851e50 (hw/arm/armsse: Move sysctl register block 
into data-driven framework)
29/54 Checking commit 722299713461 (hw/arm/armsse: Move PPUs into data-driven 
framework)
30/54 Checking commit 9fff4733371d (hw/arm/armsse: Add missing SSE-200 SYS_PPU)
31/54 Checking commit 45df2400413d (hw/arm/armsse: Indirect irq_is_common[] 
through ARMSSEInfo)
32/54 Checking commit 73393b58d18b (hw/arm/armsse: Add support for SSE variants 
with a system counter)
33/54 Checking commit c6f883cf7f1a (hw/arm/armsse: Add support for 
TYPE_SSE_TIMER in ARMSSEDeviceInfo)
34/54 Checking commit f6003eefbf67 (hw/arm/armsse: Support variants with 
ARMSSE_CPU_PWRCTRL block)
35/54 Checking commit 19c7e5298f97 (hw/arm/armsse: Add SSE-300 support)
36/54 Checking commit 34606d763c0e (hw/arm/mps2-tz: Make UART overflow IRQ 
board-specific)
37/54 Checking commit 16fac9b2dce7 (hw/misc/mps2-fpgaio: Fold counters 
subsection into main vmstate)
38/54 Checking commit 8225557a3478 (hw/misc/mps2-fpgaio: Support AN547 DBGCTRL 
register)
39/54 Checking commit 84a76c50b435 (hw/misc/mps2-scc: Implement changes for 
AN547)
40/54 Checking commit 654d5b5c6741 (hw/arm/mps2-tz: Support running APB 
peripherals on different clock)
41/54 Checking commit feee0594aeda (hw/arm/mps2-tz: Make initsvtor0 setting 
board-specific)
42/54 Checking commit b2cb63d1fe88 (hw/arm/mps2-tz: Add new mps3-an547 board)
WARNING: Block comments use a leading /* on a separate line
#145: FILE: hw/arm/mps2-tz.c:963:
+                { /* port 7 reserved */ },

WARNING: line over 80 characters
#152: FILE: hw/arm/mps2-tz.c:970:
+                { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 
0x1000 },

WARNING: line over 80 characters
#154: FILE: hw/arm/mps2-tz.c:972:
+                { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 
34, 43 } },

WARNING: line over 80 characters
#155: FILE: hw/arm/mps2-tz.c:973:
+                { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 
36, 44 } },

WARNING: line over 80 characters
#156: FILE: hw/arm/mps2-tz.c:974:
+                { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 
38, 45 } },

WARNING: line over 80 characters
#157: FILE: hw/arm/mps2-tz.c:975:
+                { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 
40, 46 } },

WARNING: line over 80 characters
#158: FILE: hw/arm/mps2-tz.c:976:
+                { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 
42, 47 } },

ERROR: line over 90 characters
#159: FILE: hw/arm/mps2-tz.c:977:
+                { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 
125, 126, 127 } },

WARNING: Block comments use a leading /* on a separate line
#161: FILE: hw/arm/mps2-tz.c:979:
+                { /* port 9 reserved */ },

total: 1 errors, 8 warnings, 223 lines checked

Patch 42/54 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

43/54 Checking commit 3c89ac98c971 (docs/system/arm/mps2.rst: Document the new 
mps3-an547 board)
44/54 Checking commit 1ae3cd272093 (tests/qtest/sse-timer-test: Add simple test 
of the SSE counter)
45/54 Checking commit bc7ce41eee2a (tests/qtest/sse-timer-test: Test the system 
timer)
46/54 Checking commit 97246f4a39cf (tests/qtest/sse-timer-test: Test counter 
scaling changes)
47/54 Checking commit f8734d1704c3 (target/arm: Restrict v7A TCG cpus to TCG 
accel)
48/54 Checking commit b52474c56a66 (hw/dma: Implement a Xilinx CSU DMA model)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51: 
new file mode 100644

total: 0 errors, 1 warnings, 808 lines checked

Patch 48/54 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
49/54 Checking commit d95d2c29b4c5 (hw/arm: xlnx-zynqmp: Clean up coding 
convention issues)
50/54 Checking commit bfdae5f8b1d0 (hw/arm: xlnx-zynqmp: Connect a Xilinx CSU 
DMA module for QSPI)
51/54 Checking commit 9e3a61006a3f (hw/ssi: xilinx_spips: Clean up coding 
convention issues)
52/54 Checking commit b9f3dfdc6961 (hw/ssi: xilinx_spips: Remove DMA related 
dead codes from zynqmp_spips)
53/54 Checking commit fea8e80265e6 (hw/timer/renesas_tmr: Prefix constants for 
CSS values with CSS_)
54/54 Checking commit 07374e1311fb (hw/timer/renesas_tmr: Fix use of 
uninitialized data in read_tcnt())
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20210308173244.20710-1-peter.maydell@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20210308173244.20710-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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