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[PULL 13/49] target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
From: |
Peter Maydell |
Subject: |
[PULL 13/49] target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks |
Date: |
Fri, 5 Mar 2021 17:14:39 +0000 |
From: Peter Collingbourne <pcc@google.com>
Section D6.7 of the ARM ARM states:
For the purpose of determining Tag Check Fault handling, unprivileged
load and store instructions are treated as if executed at EL0 when
executed at either:
- EL1, when the Effective value of PSTATE.UAO is 0.
- EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}
and the Effective value of PSTATE.UAO is 0.
ARM has confirmed a defect in the pseudocode function
AArch64.TagCheckFault that makes it inconsistent with the above
wording. The remedy is to adjust references to PSTATE.EL in that
function to instead refer to AArch64.AccessUsesEL(acctype), so
that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1.
The exception type for synchronous tag check faults remains unchanged.
This patch implements the described change by partially reverting
commits 50244cc76abc and cc97b0019bb5.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219201820.2672077-1-pcc@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 2 +-
target/arm/mte_helper.c | 13 +++++++++----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index fedcf2e739e..904b0927cd2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13170,7 +13170,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env,
int el, int fp_el,
if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
&& tbid
&& !(env->pstate & PSTATE_TCO)
- && (sctlr & SCTLR_TCF)
+ && (sctlr & SCTLR_TCF0)
&& allocation_tag_access_enabled(env, 0, sctlr)) {
flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
}
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 1c569336eae..0bbb9ec3463 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -550,10 +550,14 @@ static void mte_check_fail(CPUARMState *env, uint32_t
desc,
reg_el = regime_el(env, arm_mmu_idx);
sctlr = env->cp15.sctlr_el[reg_el];
- el = arm_current_el(env);
- if (el == 0) {
+ switch (arm_mmu_idx) {
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E20_0:
+ el = 0;
tcf = extract64(sctlr, 38, 2);
- } else {
+ break;
+ default:
+ el = reg_el;
tcf = extract64(sctlr, 40, 2);
}
@@ -570,7 +574,8 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
env->exception.vaddress = dirty_ptr;
is_write = FIELD_EX32(desc, MTEDESC, WRITE);
- syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11);
+ syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0,
+ is_write, 0x11);
raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));
/* noreturn, but fall through to the assert anyway */
--
2.20.1
- [PULL 08/49] tests/qtests: Add npcm7xx emc model test, (continued)
- [PULL 08/49] tests/qtests: Add npcm7xx emc model test, Peter Maydell, 2021/03/05
- [PULL 12/49] virtio-mmio: improve virtio-mmio get_dev_path alog, Peter Maydell, 2021/03/05
- [PULL 05/49] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU, Peter Maydell, 2021/03/05
- [PULL 07/49] hw/arm: Add npcm7xx emc model, Peter Maydell, 2021/03/05
- [PULL 11/49] hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init(), Peter Maydell, 2021/03/05
- [PULL 06/49] hw/net: Add npcm7xx emc model, Peter Maydell, 2021/03/05
- [PULL 10/49] target/arm: Speed up aarch64 TBL/TBX, Peter Maydell, 2021/03/05
- [PULL 09/49] hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property, Peter Maydell, 2021/03/05
- [PULL 17/49] hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces, Peter Maydell, 2021/03/05
- [PULL 18/49] hw/display/tc6393xb: Expand out macros in template header, Peter Maydell, 2021/03/05
- [PULL 13/49] target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks,
Peter Maydell <=
- [PULL 15/49] target/arm/cpu: Update coding style to make checkpatch.pl happy, Peter Maydell, 2021/03/05
- [PULL 14/49] target/arm: Restrict v8M IDAU to TCG, Peter Maydell, 2021/03/05
- [PULL 16/49] hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces, Peter Maydell, 2021/03/05
- [PULL 20/49] hw/display/omap_lcdc: Expand out macros in template header, Peter Maydell, 2021/03/05
- [PULL 19/49] hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite, Peter Maydell, 2021/03/05
- [PULL 22/49] hw/display/omap_lcdc: Fix coding style issues in template header, Peter Maydell, 2021/03/05
- [PULL 29/49] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board, Peter Maydell, 2021/03/05
- [PULL 23/49] hw/display/omap_lcdc: Inline template header into C file, Peter Maydell, 2021/03/05
- [PULL 21/49] hw/display/omap_lcdc: Drop broken bigendian ifdef, Peter Maydell, 2021/03/05
- [PULL 24/49] hw/display/omap_lcdc: Delete unnecessary macro, Peter Maydell, 2021/03/05