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[PATCH v3 32/42] esp: latch individual bits in ESP_RINTR register
From: |
Mark Cave-Ayland |
Subject: |
[PATCH v3 32/42] esp: latch individual bits in ESP_RINTR register |
Date: |
Thu, 4 Mar 2021 22:10:53 +0000 |
Currently the ESP_RINTR register is set to a specific value as required within
the ESP state machine. In order to implement the upcoming deferred interrupt
functionality it is necessary to set individual bits within ESP_RINTR so that
a deferred interrupt will not overwrite the value of any other interrupt bits.
This also requires fixing up a few locations where the ESP_RINTR and ESP_RSEQ
registers are set/reset unexpectedly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
---
hw/scsi/esp.c | 29 +++++++++++++----------------
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 6aae6f91c2..54d008c609 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -178,7 +178,7 @@ static int esp_select(ESPState *s)
if (!s->current_dev) {
/* No such drive */
s->rregs[ESP_RSTAT] = 0;
- s->rregs[ESP_RINTR] = INTR_DC;
+ s->rregs[ESP_RINTR] |= INTR_DC;
s->rregs[ESP_RSEQ] = SEQ_0;
esp_raise_irq(s);
return -1;
@@ -245,7 +245,7 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t
busid)
}
scsi_req_continue(s->current_req);
}
- s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
+ s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_raise_irq(s);
esp_lower_drq(s);
@@ -326,7 +326,7 @@ static void satn_stop_pdma_cb(ESPState *s)
trace_esp_handle_satn_stop(s->cmdlen);
s->do_cmd = 1;
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
- s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
+ s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_raise_irq(s);
}
@@ -346,8 +346,8 @@ static void handle_satn_stop(ESPState *s)
trace_esp_handle_satn_stop(s->cmdlen);
s->cmdlen = cmdlen;
s->do_cmd = 1;
- s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
- s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
+ s->rregs[ESP_RSTAT] = STAT_CD;
+ s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_raise_irq(s);
} else if (cmdlen == 0) {
@@ -362,7 +362,7 @@ static void handle_satn_stop(ESPState *s)
static void write_response_pdma_cb(ESPState *s)
{
s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
- s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
+ s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_raise_irq(s);
}
@@ -376,7 +376,7 @@ static void write_response(ESPState *s)
if (s->dma_memory_write) {
s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
- s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
+ s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
} else {
s->pdma_cb = write_response_pdma_cb;
@@ -395,7 +395,7 @@ static void write_response(ESPState *s)
static void esp_dma_done(ESPState *s)
{
s->rregs[ESP_RSTAT] |= STAT_TC;
- s->rregs[ESP_RINTR] = INTR_BS;
+ s->rregs[ESP_RINTR] |= INTR_BS;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
esp_set_tc(s, 0);
@@ -700,7 +700,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
val = s->rregs[ESP_RINTR];
s->rregs[ESP_RINTR] = 0;
s->rregs[ESP_RSTAT] &= ~STAT_TC;
- s->rregs[ESP_RSEQ] = SEQ_CD;
+ s->rregs[ESP_RSEQ] = SEQ_0;
esp_lower_irq(s);
if (s->deferred_complete) {
esp_report_command_complete(s, s->deferred_status);
@@ -771,9 +771,6 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t
val)
/*s->ti_size = 0;*/
s->ti_wptr = 0;
s->ti_rptr = 0;
- s->rregs[ESP_RINTR] = INTR_FC;
- s->rregs[ESP_RSEQ] = 0;
- s->rregs[ESP_RFLAGS] = 0;
break;
case CMD_RESET:
trace_esp_mem_writeb_cmd_reset(val);
@@ -781,8 +778,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t
val)
break;
case CMD_BUSRESET:
trace_esp_mem_writeb_cmd_bus_reset(val);
- s->rregs[ESP_RINTR] = INTR_RST;
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
+ s->rregs[ESP_RINTR] |= INTR_RST;
esp_raise_irq(s);
}
break;
@@ -793,12 +790,12 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t
val)
case CMD_ICCS:
trace_esp_mem_writeb_cmd_iccs(val);
write_response(s);
- s->rregs[ESP_RINTR] = INTR_FC;
+ s->rregs[ESP_RINTR] |= INTR_FC;
s->rregs[ESP_RSTAT] |= STAT_MI;
break;
case CMD_MSGACC:
trace_esp_mem_writeb_cmd_msgacc(val);
- s->rregs[ESP_RINTR] = INTR_DC;
+ s->rregs[ESP_RINTR] |= INTR_DC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
esp_raise_irq(s);
@@ -806,7 +803,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t
val)
case CMD_PAD:
trace_esp_mem_writeb_cmd_pad(val);
s->rregs[ESP_RSTAT] = STAT_TC;
- s->rregs[ESP_RINTR] = INTR_FC;
+ s->rregs[ESP_RINTR] |= INTR_FC;
s->rregs[ESP_RSEQ] = 0;
break;
case CMD_SATN:
--
2.20.1
- [PATCH v3 22/42] esp: move PDMA length adjustments into esp_pdma_read()/esp_pdma_write(), (continued)
- [PATCH v3 22/42] esp: move PDMA length adjustments into esp_pdma_read()/esp_pdma_write(), Mark Cave-Ayland, 2021/03/04
- [PATCH v3 23/42] esp: use ti_wptr/ti_rptr to manage the current FIFO position for PDMA, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 24/42] esp: use in-built TC to determine PDMA transfer length, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 25/42] esp: remove CMD pdma_origin, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 26/42] esp: rename get_cmd_cb() to esp_select(), Mark Cave-Ayland, 2021/03/04
- [PATCH v3 27/42] esp: fix PDMA target selection, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 28/42] esp: use FIFO for PDMA transfers between initiator and device, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 29/42] esp: remove pdma_origin from ESPState, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 30/42] esp: add 4 byte PDMA read and write transfers, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 31/42] esp: implement FIFO flush command, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 32/42] esp: latch individual bits in ESP_RINTR register,
Mark Cave-Ayland <=
- [PATCH v3 33/42] esp: defer command completion interrupt on incoming data transfers, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 34/42] esp: remove old deferred command completion mechanism, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 35/42] esp: raise interrupt after every non-DMA byte transferred to the FIFO, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 36/42] esp: add maxlen parameter to get_cmd(), Mark Cave-Ayland, 2021/03/04
- [PATCH v3 37/42] esp: transition to message out phase after SATN and stop command, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 38/42] esp: convert ti_buf from array to Fifo8, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 39/42] esp: convert cmdbuf from array to Fifo8, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 40/42] esp: add trivial implementation of the ESP_RFLAGS register, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 41/42] esp: implement non-DMA transfers in PDMA mode, Mark Cave-Ayland, 2021/03/04
- [PATCH v3 42/42] esp: add support for unaligned accesses, Mark Cave-Ayland, 2021/03/04